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PDF VNQ7050AJ-E Data sheet ( Hoja de datos )
| Número de pieza | VNQ7050AJ-E | |
| Descripción | Quad channel high-side driver | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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VNQ7050AJ-E
Quad channel high-side driver with CurrentSense analog feedback
for automotive applications
Datasheet - production data
PowerSSO-16
GAPGCFT00327
– Configurable latch-off on overtemperature
or power limitation with dedicated fault
reset pin
– Loss of ground and loss of VCC
– Reverse battery with external components
– Electrostatic discharge protection
Features
Max transient supply voltage
VCC
Operating voltage range
VCC
Typ. on-state resistance (per Ch) RON
Current limitation (typ)
ILIMH
Stand-by current (max)
ISTBY
40 V
4 to 28 V
50 mΩ
27 A
0.5 µA
• Automotive qualified
• General
– Quad channel smart high-side driver with
CS analog feedback
– Very low standby current
– Compatible with 3 V and 5 V CMOS
outputs
• CurrentSense diagnostic functions
– Analog feedback of load current with high
precision proportional current mirror
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
– OFF-state open-load detection
– Output short to VCC detection
– Sense enable/disable
• Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
Applications
• All types of automotive resistive, inductive and
capacitive loads
• Specially intended for automotive signal lamps
(up to P27W or SAE1156 or LED Real
Combinations)
Description
The VNQ7050AJ-E is a quad channel high-side
driver manufactured using ST proprietary
VIPower® technology and housed in
PowerSSO-16 package. The device is designed
to drive 12 V automotive grounded loads through
a 3 V and 5 V CMOS-compatible interface,
providing protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
October 2014
This is information on a product in full production.
DocID023258 Rev 7
1/43
www.st.com
1 page  
VNQ7050AJ-E
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Switching times and Pulse skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Current sense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TDSKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) . . . . . . . . . . . 19
Latch functionality - behavior in hard short circuit condition . . . . . . . . . . . . . . . . . . . . . . . . 19
Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) 20
Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Standby state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
IGND(ON) vs Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Logic Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Logic Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Logic Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FaultRST Input clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
On-state resistance vs Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Won vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Woff vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
OFF-state open-load voltage detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Vsense clamp vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Vsenseh vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Current sense and diagnostic – block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Current sense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Analogue HSD – open-load detection in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . . 35
PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . . . 35
Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . . 36
PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) . . . . . 36
Thermal fitting model of a double-channel HSD in PowerSSO-16 . . . . . . . . . . . . . . . . . . . 37
PowerSSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DocID023258 Rev 7
5/43
5
5 Page 
VNQ7050AJ-E
Electrical specification
Table 6. Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified)
Symbol
Parameter
Test conditions Min. Typ. Max. Unit
td(on)(1)
td(off)(1)
Turn-on delay time at Tj = 25°C
Turn-off delay time at Tj = 25°C
(dVOUT/dt)on(1)
Turn-on voltage slope at
Tj = 25°C
(dVOUT/dt)off(1)
Turn-off voltage slope at
Tj = 25°C
WON
Switching energy losses at turn-
on (twon)
WOFF
Switching energy losses at turn-
off (twoff)
tSKEW(1)
Differential Pulse skew
(tPHL - tPLH)
RL = 6.5 Ω
RL = 6.5 Ω
RL = 6.5 Ω
RL = 6.5 Ω
RL = 6.5 Ω
10 35 120
µs
10 45 100
0.1 0.28
0.1 0.31
0.7
V/µs
0.7
— 0.26 0.35(2) mJ
— 0.23 0.31(2) mJ
-40 10 60 µs
1. See Figure 4: Switching times and Pulse skew.
2. Parameter guaranteed by design and characterization, not subject to production test
Symbol
Table 7. Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C)
Parameter
Test conditions Min. Typ. Max. Unit
INPUT0,1,2,3 characteristics
VIL
IIL
VIH
IIH
VI(hyst)
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
VICL
Input clamp voltage
FaultRST characteristics
VFRL
IFRL
VFRH
IFRH
VFR(hyst)
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
VFRCL Input clamp voltage
SEL0,1 characteristics (7 V < VCC < 18 V)
VSELL
ISELL
Input low level voltage
Low level input current
VIN = 0.9 V
VIN = 2.1 V
IIN = 1 mA
IIN = -1 mA
VIN = 0.9 V
VIN = 2.1 V
IIN = 1 mA
IIN = -1 mA
VIN = 0.9 V
0.9
1
2.1
10
0.2
5.3 7.2
-0.7
V
µA
V
µA
V
V
0.9
1
2.1
10
0.2
5.3 7.5
-0.7
V
µA
V
µA
V
V
0.9 V
1 µA
DocID023258 Rev 7
11/43
42
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet VNQ7050AJ-E.PDF ] | |
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