PDF KSZ8021RNL Data sheet ( Hoja de datos )

Número de pieza	KSZ8021RNL
Descripción	10Base-T/100Base-TX PHY
Fabricantes	Micrel Semiconductor
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No Preview Available ! KSZ8021RNL / KSZ8031RNL 10Base-T/100Base-TX PHY with RMII Support General Description Features The KSZ8031RNL is a single-supply 10Base-T/100Base- TX Ethernet physical layer transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable. The KSZ8031RNL is a highly-integrated, compact solution. It reduces board cost and simplifies board layout by using on-chip termination resistors for the differential pairs, by integrating a low noise regulator to supply the 1.2V core, and by offering 1.8/2.5/3.3V digital I/O interface support. The KSZ8031RNL offers the Reduced Media Independent Interface (RMII) for direct connection to RMII-compliant MACs in Ethernet processors and switches. As the power-up default, the KSZ8031RNL uses a 25MHz crystal to generate all required clocks, including the 50MHz RMII reference clock output for the MAC. The KSZ8021RNL is the version that takes in the 50MHz RMII reference clock as the power-up default. To facilitate system bring-up and debugging in production testing and in product deployment, parametric NAND tree support enables fault detection between KSZ8031RNL I/Os and board, while Micrel’s LinkMD® TDR-based cable diagnostics permit identification of faulty copper cabling. The KSZ8031RNL and KSZ8021RNL are available in 24- pin, lead-free QFN packages (see Ordering Information). Data sheets and support documentation can be found on Micrel’s web site at: www.micrel.com. • Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet Transceiver • RMII v1.2 Interface support with 50MHz reference clock output to MAC, and option to input 50MHz reference clock • RMII back-to-back mode support for 100Mbps copper repeater or media converter • MDC/MDIO Management Interface for PHY register configuration • Programmable interrupt output • LED outputs for link and activity status indication • On-chip termination resistors for the differential pairs • Baseline Wander Correction • HP Auto MDI/MDI-X for reliable detection and correction for straight-through and crossover cables with disable and enable option • Auto-negotiation to automatically select the highest link- up speed (10/100 Mbps) and duplex (half/full) • Power down and power saving modes • LinkMD® TDR-based cable diagnostics for identification of faulty copper cabling • Parametric NAND Tree support for fault detection between chip I/Os and board ____________________________________________________________________________________________________________ Functional Diagram LinkMD is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com August 2010 M9999-082710-1.0 1 page Micrel, Inc. KSZ8021RNL / KSZ8031RNL NAND Tree Support ............................................................................................................................................................ 21 NAND Tree I/O Testing..................................................................................................................................................... 22 Power Management ............................................................................................................................................................ 22 Power Saving Mode.......................................................................................................................................................... 22 Energy Detect Power Down Mode ................................................................................................................................... 22 Power Down Mode ........................................................................................................................................................... 22 Slow Oscillator Mode ........................................................................................................................................................ 23 Reference Circuit for Power and Ground Connections .................................................................................................. 23 Register Map........................................................................................................................................................................ 24 Register Description ........................................................................................................................................................... 24 Register Description (Continued)...................................................................................................................................... 25 Register Description (Continued)...................................................................................................................................... 26 Register Description (Continued)...................................................................................................................................... 27 Register Description (Continued)...................................................................................................................................... 28 Register Description (Continued)...................................................................................................................................... 29 Register Description (Continued)...................................................................................................................................... 30 Register Description (Continued)...................................................................................................................................... 31 Register Description (Continued)...................................................................................................................................... 32 Absolute Maximum Ratings(1) ............................................................................................................................................ 33 Operating Ratings(2) ............................................................................................................................................................ 33 Electrical Characteristics(3) ................................................................................................................................................ 33 Electrical Characteristics(3) (Continued) ........................................................................................................................... 34 Timing Diagrams ................................................................................................................................................................. 35 RMII Timing....................................................................................................................................................................... 35 Auto-Negotiation Timing ................................................................................................................................................... 36 MDC/MDIO Timing ........................................................................................................................................................... 37 Reset Timing..................................................................................................................................................................... 38 Reset Circuit ........................................................................................................................................................................ 39 Reference Circuit for LED Strapping Pin.......................................................................................................................... 40 Magnetics Specification ..................................................................................................................................................... 41 Reference Clock – Connection and Selection.................................................................................................................. 41 Package Information........................................................................................................................................................... 43 August 2010 5 M9999-082710-1.0 5 Page Micrel, Inc. KSZ8021RNL / KSZ8031RNL Strapping Options – KSZ8021RNL / KSZ8031RNL Pin Number Pin Name 15 PHYAD[1:0] 23 ANEN_SPEED Type(1) Ipd/O Ipu/O Pin Function The PHY Address is latched at the de-assertion of reset and is configurable to either one of the following two values: Pull-up = PHY Address is set to 00011b (0x3h) Pull-down (default) = PHY Address is set to 00000b (0x0h) PHY Address bits [4:2] are set to ‘000’ by default. Auto-Negotiation Enable and SPEED mode Pull-up (default) = Enable Auto-Negotiation and set 100Mbps Speed Pull-down = Disable Auto-Negotiation and set 10Mbps Speed At the de-assertion of reset, this pin value is latched into register 0h bit [12] for Auto- negotiation enable/disable, register 0h bit [13] for the Speed select, and register 4h (Auto-Negotiation Advertisement) for the Speed capability support. Note: 1. Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. The PHYAD[1:0] strap-in pin is latched at the de-assertion of reset. In some systems, the RMII MAC receive input pin may drive high/low during power-up or reset, and consequently cause the PHYAD[1:0] strap-in pin, a shared pin with the RMII CRS_DV signal, to be latched to the unintended high/low states. In this case, an external pull-up (4.7K) or pull-down (1.0K) should be added on the PHYAD[1:0] strap-in pin to ensure the intended value is strapped-in correctly. August 2010 11 M9999-082710-1.0 11 Page

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