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PDF KSZ8692PB Data sheet ( Hoja de datos )

Número de pieza KSZ8692PB
Descripción Integrated Networking and Communications Controller
Fabricantes Micrel Semiconductor 
Logotipo Micrel Semiconductor Logotipo



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No Preview Available ! KSZ8692PB Hoja de datos, Descripción, Manual

KSZ8692PB, KSZ8692PB-S
Integrated Networking and
Communications Controller
Rev. 5.0
General Description
The KSZ8692PB, KSZ8692PB-S is a highly integrated
System-on-Chip (SoC) containing an ARM 922T 32-bit
processor and a rich set of peripherals to address the cost-
sensitive, high-performance needs of a wide variety of high
bandwidth networking and communications applications.
The KSZ9692PB-S is a small package version of
KSZ9692PB and it supports 16 bit DDR data width.
Features
ARM 922T High-Performance Processor Core
250 MHz ARM 922T RISC processor core
8KB I-cache and 8KB D-cache
Configurable Memory Management Unit (MMU) for
Linux and WinCE
Memory Controller
8/16-bit external bus interface for FLASH, ROM, SRAM,
and external I/O
NAND FLASH controller
200MHz 32-bit DDR controller
Two JEDEC Specification JESD82-1 compliant
differential clock drivers for a glueless DDR interface
solution
Ethernet Interfaces
Two Ethernet (10/100 Mbps) MACs
MII interface
Fully compliant with IEEE 802.3 Ethernet standards
IP Security Engine
Hardware IPSec Engine guarantees 100Mbps VPN
Secure Socket Layer Support
DES/3DES/AES/RC4 Cyphers
MD-5, SHA-1, SHA-256 Hashing Algorithms
HMAC
SSLMAC
PCI Interface
Version PCI 2.3
32-bit 33/66MHz
Integrated PCI Arbiter supports three external masters
Configurable as Host bridge or Guest device
Glueless Support for mini-PCI or CardBus devices
Dual High Speed USB 2.0 Interfaces
Two USB2.0 ports with integrated PHY
Can be configured as 2-port host, or host + device
SDIO/SD Host Controller
Meets SD Host Controller Standard Specification
Version 1.0
Meets SDIO card specification Version 1.0
DMA Controllers
Dedicated DMA channels for PCI, USB, IPSec, SDIO
and Ethernet ports.
Peripherals
Four high-speed UART ports up to 5 Mbps
Two programmable 32-bit timers with watchdog timer
capability
Interrupt Controller
Twenty GPIO ports
One shared SPI/I2C interface
One I2S port
Debugging
ARM9 JTAG debug interface
JTAG Boundary Scan Support
Power Management
CPU and system clock speed step-down options
Ethernet port Wake-on-LAN
DDR and PCI power down
Operating Voltage
1.3V power for core
3.3V power for I/O
2.5V or 2.6V power for DDR memory interface
Reference Hardware and Software Evaluation Kit
Hardware evaluation Kit
Software Evaluation Kit includes WinCE BSP, Open
WRT BSP, Linux based SOHO Router packages
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
May 2011
M9999-051111-4.0

1 page




KSZ8692PB pdf
Micrel, Inc.
KSZ8692PB, KSZ8692PB-S
Contents
System Level Applications ...................................................................................................................................................... 8
Functional Description........................................................................................................................................................... 25
ARM High-Performance Processor................................................................................................................................... 26
FLASH/ROM/SRAM Memory and External I/O Interface.................................................................................................. 26
NAND Flash Memory Interface ......................................................................................................................................... 28
DDR Controller .................................................................................................................................................................. 29
SDIO/SD Host Controller .................................................................................................................................................. 33
IP Security Engine............................................................................................................................................................. 33
USB 2.0 Interface .............................................................................................................................................................. 34
PCI Interface ..................................................................................................................................................................... 35
Ethernet MAC Ports (Port 0 = WAN, Port 1 = LAN).......................................................................................................... 35
Wake-on-LAN .............................................................................................................................................................. 35
Link Change ................................................................................................................................................................ 36
Wake-up Packet .......................................................................................................................................................... 36
Magic Packet ............................................................................................................................................................... 36
IPv6 Support................................................................................................................................................................ 37
DMA Controller ............................................................................................................................................................... 37
UART Interface ............................................................................................................................................................... 37
Timers and Watchdog..................................................................................................................................................... 37
GPIO ............................................................................................................................................................................... 37
I2C .................................................................................................................................................................................. 37
SPI .................................................................................................................................................................................. 38
I2S................................................................................................................................................................................... 38
Interrupt Controller.......................................................................................................................................................... 38
System Level Interfaces ................................................................................................................................................. 39
Power-up Strapping Options .......................................................................................................................................... 21
Absolute Maximum Ratings .................................................................................................................................................. 25
Operating Ratings ................................................................................................................................................................. 40
Electrical Characteristics....................................................................................................................................................... 40
Timing Specifications ............................................................................................................................................................ 41
Signal Location Information................................................................................................................................................... 44
Package Information ............................................................................................................................................................. 45
May, 2011
5 M9999-051111-4.0

5 Page





KSZ8692PB arduino
Micrel, Inc.
KSZ8692PB, KSZ8692PB-S
Pin Description: Signal Description by Group (Continued)
Pin Number
Pin Name
Pin Type Pin Description
U3
NWPN
Ipu/O
NAND Write Protection, asserted low
P4, U4
NRBN[1:0]
I NAND Ready/Busy, asserted low for busy.
DDR Interface
T17, V18,
U17, T16,
W20, W19,
Y20, Y19,
W18, V17,
U16, T15,
Y18, V16
DADDR[13..0]
V13, U11,
V12, W13,
Y13, W12,
V11, U10,
V10, Y11,
W10, U9,
Y10, V9, W9,
Y9, W8, Y8,
Y7, W7, V7,
Y6, W6, V6,
Y5, V5, W5,
U5, T5, Y4,
V4, W4
DDATA[31..0]
T13, V14
BA[1:0]
U14 CSN
T14
U15
V15
T12, Y12,
U8, T6
RASN
CASN
WEN
DM[3:0]
U12, W11,
V8, U6
DQS[3:0]
O DDR Address Bus.
I/O DDR Data Bus.
O DDR Bank Address.
O DDR Chip Select, asserted Low.
Chip select pins for DDR, the KSZ8692PB, KSZ8692PB-S supports only one
DDR bank.
O DDR Row Address Strobe, asserted Low.
The Row Address Strobe pin for DDR.
O DDR Column Address Strobe, asserted Low.
The Column Address Strobe pin for DDR.
O DDR Write Enable, asserted Low.
The write enable signal for DDR.
O DDR Data Input/Output Mask
Data Input/Output mask signals for DDR. DM is sampled High and is an output
mask signal for write accesses and an output enable signal for read accesses.
Input data is masked during a Write cycle. DM0 corresponds to DDATA[7:0],
DM1 corresponds to DDATA[15:8], DM2 corresponds to DDATA[23:16] and
DM3 corresponds to DDATA[31:24].
I/O DDR only Data Strobe
Input with read data, output with write data. DQS0 corresponds to DDATA[7:0],
DQS1 corresponds to DDATA[15:8], DQS2 corresponds to DDATA[23:16] and
DQS3 corresponds to DDATA[31:24].
Ethernet Port 0
M16 P0_RXC
May, 2011
Ipd/O
MAC mode MII: input RX clock
PHY mode MII: output RX clock
11
M9999-051111-4.0

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