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PDF KSZ8864RMN Data sheet ( Hoja de datos )

Número de pieza KSZ8864RMN
Descripción Integrated 4-Port 10/100 Managed Switch
Fabricantes Micrel Semiconductor 
Logotipo Micrel Semiconductor Logotipo



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KSZ8864RMN
Integrated 4-Port 10/100 Managed Switch
with Two MACs MII or RMII Interfaces
Rev 1.5
General Description
The KSZ8864RMN is a highly-integrated, Layer 2
managed 4-port switch with optimized design, plentiful
features and smallest package size. It is designed for cost-
sensitive 10/100Mbps 4-port switch systems with on-chip
termination, lowest-power consumption, and small
package to save system cost. It has 1.4Gbps high-
performance memory bandwidth, shared memory-based
switch fabric with full non-blocking configuration. It also
provides an extensive feature set such as the power
management, programmable rate limiting and priority ratio,
tag/port-based VLAN, packet filtering, quality of service
(QoS), four queue prioritization, management interface,
MIB counters. Port 3 and Port 4 support either MII or RMII
interfaces with SW3-MII/RMII and SW4-MII/RMII (see
Functional Diagram) for KSZ8864RMN data interface. An
industrial temperature-grade version of the KSZ8864RMNI
and a qualified AEC-Q100 Automotive version of the
KSZ8864RMNU are also available (see “Ordering
Information” section).The KSZ8864RMN provides multiple
CPU control/data interfaces to effectively address both
current and emerging fast Ethernet applications.
The KSZ8864RMN consists of 10/100 fast Ethernet PHYs
with patented and enhanced mixed-signal technology,
media access control (MAC) units, a high-speed non-
blocking switch fabric, a dedicated address lookup engine,
and an on-chip frame buffer memory.
The KSZ8864RMN contains four MACs and two PHYs.
The two PHYs support the 10/100Base-T/TX.
All registers of MACs and PHYs units can be managed by
the control interface of SPI or the SMI. MIIM registers of
the PHYs can be accessed through the MDC/MDIO
interface. EEPROM can set all control registers by I2C
controller interface for the unmanaged mode.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Diagram
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
April 2012
M9999-043012-1.5

1 page




KSZ8864RMN pdf
Micrel, Inc.
KSZ8864RMN
Broadcast Storm Protection.............................................................................................................................................. 29
MII Interface Operation ..................................................................................................................................................... 29
Switch MAC3/MAC4 SW3/SW4-MII Interface .................................................................................................................. 29
Switch MAC3/MAC4 SW3/SW4-RMII Interface................................................................................................................ 31
Advanced Functionality ......................................................................................................................................................... 33
Spanning Tree Support..................................................................................................................................................... 34
Rapid Spanning Tree Support .......................................................................................................................................... 35
Tail Tagging Mode ............................................................................................................................................................ 36
IGMP Support ................................................................................................................................................................... 37
Port Mirroring Support ...................................................................................................................................................... 37
VLAN Support ................................................................................................................................................................... 37
Rate Limiting Support ....................................................................................................................................................... 38
Ingress Rate Limit ............................................................................................................................................................. 38
Egress Rate Limit.............................................................................................................................................................. 39
Transmit Queue Ratio Programming ................................................................................................................................ 39
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast ........................ 39
Configuration Interface ..................................................................................................................................................... 39
SPI Slave Serial Bus Configuration .................................................................................................................................. 40
MII Management Interface (MIIM) .................................................................................................................................... 43
Serial Management Interface (SMI).................................................................................................................................. 43
Register Description.............................................................................................................................................................. 45
Global Registers ............................................................................................................................................................... 46
Port Registers ................................................................................................................................................................... 56
Advanced Control Registers ............................................................................................................................................. 65
Data Rate Selection Table in 100BT ................................................................................................................................ 80
Data Rate Selection Table in 10BT .................................................................................................................................. 81
Static MAC Address Table .................................................................................................................................................... 83
VLAN Table ........................................................................................................................................................................... 86
Dynamic MAC Address Table ............................................................................................................................................... 89
MIB (Management Information Base) Counters ................................................................................................................... 91
For Port 1 .......................................................................................................................................................................... 91
All Ports Dropped Packet MIB Counters .......................................................................................................................... 92
Format of “All Dropped Packet” MMIB Counter................................................................................................................ 92
MIIM Registers ...................................................................................................................................................................... 94
Absolute Maximum Ratings .................................................................................................................................................. 98
Operating Ratings ................................................................................................................................................................. 98
Electrical Characteristics....................................................................................................................................................... 98
April 2012
5 M9999-043012-1.5

5 Page





KSZ8864RMN arduino
Micrel, Inc.
KSZ8864RMN
Pin Description (Continued)
Pin Number
Pin Name
Type(1)
26
SM3RXD2
IPD/O
27
SM3RXD1
IPD/O
28
SM3RXD0
IPD/O
29
SM3CRS
IPD/O
30
GND
GND
31
SM3COL
IPD/O
32
SM4TXEN
IPD
33
SM4TXD3
IPD
34
SM4TXD2
IPD
35
SM4TXD1
IPD
36
SM4TXD0
IPD
37
SM4TXC/SM4REFCLK
I/O
38
VDDIO
P
39
SM4RXC
I/O
Port
3
3
3
3
3
4
4
4
4
4
4
4
Pin Function(2)
MAC3 Switch MII receive bit 2 and Strap option:
PD (default) = disable back pressure;
PU = enable back pressure.
MAC3 Switch MII/RMII receive bit 1.
Strap option:
PD (default) = drop excessive collision packets;
PU = does not drop excessive collision packets.
MAC3 Switch MII/RMII receive bit 0.
Strap option:
PD (default) = disable aggressive back-off algorithm in half-duplex
mode;
PU = enable for performance enhancement.
MAC3 Switch MII carrier sense.
Ground with all grounding of die bottom.
MAC3 Switch MII collision detect.
MAC4 Switch MII/RMII transmit enable.
MAC4 Switch MII transmit bit 3.
MAC4 Switch MII transmit bit 2.
MAC4 Switch MII/RMII transmit bit 1.
MAC4 Switch MII/RMII transmit bit 0.
MAC4 Switch MII transmit clock:
Input: SW4-MII MAC mode clock.
Input: SW4-RMII reference clock, please also see the strap-in pin
P1LED1 for the clock mode and normal mode.
Output: SW4-MII PHY modes.
3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
MAC4 Switch MII Receive clock:
Input: SW4-MII MAC mode.
Output: SW4-MII PHY mode.
Output: SW4-RMII 50MHz reference clock (the device is default clock
mode, the clock source comes from X1/X2 pins 25MHz crystal).
When set the device as normal mode (the chip’s clock source comes
from SM4TXC), the SM4RXC reference clock output should be
disabled by the register 87. Please also see the strap-in pin P1LED1
for the selection of the clock mode and normal mode.
April 2012
11 M9999-043012-1.5

11 Page







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