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PDF KSZ8851-32MQLI Data sheet ( Hoja de datos )

Número de pieza KSZ8851-32MQLI
Descripción Single-Port Ethernet MAC Controller
Fabricantes Micrel Semiconductor 
Logotipo Micrel Semiconductor Logotipo



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KSZ8851-16/32MQL/MQLI
Single-Port Ethernet MAC Controller
with 8/16-Bit or 32-Bit Non-PCI Interface
Rev. 2.0
General Description
The KSZ8851M-series is a single-port controller chip with
a non-PCI CPU interface and is available in 8/16-bit and
32-bit bus designs. This datasheet describes the 128-pin
PQFP KSZ8851-16/32MQL for applications requiring high-
performance from single-port Ethernet Controller with
8/16-bit or 32-bit generic processor interface. The
KSZ8851M offers the most cost-effective solution for
adding high-throughput Ethernet connectivity to traditional
embedded systems.
The KSZ8851M is a single chip, mixed analog/digital
device offering Wake-on-LAN technology for effectively
addressing Fast Ethernet applications. It consists of a Fast
Ethernet MAC controller, an 8-bit, 16-bit and 32-bit generic
host processor interface and incorporates a unique
dynamic memory pointer with 4-byte buffer boundary and
a fully utilizable 18KB for both TX (allocated 6KB) and RX
(allocated 12KB) directions in host buffer interface.
The KSZ8851M is designed to be fully compliant with the
appropriate IEEE 802.3 standards. An industrial
temperature-grade version of the KSZ8851M, the
KSZ8851MQLI is also available (see “Ordering Information
section).
Functional Diagram
LinkMD®
Physical signal transmission and reception are enhanced
through the use of analog circuitry, making the design
more efficient and allowing for lower-power consumption.
The KSZ8851M is designed using a low-power CMOS
process that features a single 3.3V power supply with
options for 1.8V, 2.5V or 3.3V VDD I/O. The device
includes an extensive feature set that offers management
information base (MIB) counters and CPU control/data
interfaces with single bus timing.
The KSZ8851M includes unique cable diagnostics feature
called LinkMD®. This feature determines the length of the
cabling plant and also ascertains if there is an open or
short condition in the cable. Accompanying software
enables the cable length and cable conditions to be
conveniently displayed. In addition, the KSZ8851M
supports Hewlett Packard (HP) Auto-MDIX thereby
eliminating the need to differentiate between straight or
crossover cables in applications.
Figure 1. KSZ8851-16/32MQL/MQLI Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Magic Packet is a trademark of Advanced Micro Devices, Inc.
Product names used in this datasheet are for identification purposes
only and may be trademarks of their respective companies.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2009
M9999-083109-2.0

1 page




KSZ8851-32MQLI pdf
Micrel, Inc.
KSZ8851-16/32 MQL/MQLI
Transmit Queue (TXQ) Frame Format ........................................................................................................................... 33
Frame Transmitting Path Operation in TXQ ................................................................................................................... 34
Driver Routine for Transmit Packet from Host Processor to KSZ8851M ....................................................................... 35
Receive Queue (RXQ) Frame Format............................................................................................................................ 38
Frame Receiving Path Operation in RXQ....................................................................................................................... 38
Driver Routine for Receive Packet from KSZ8851M to Host Processor ........................................................................ 39
EEPROM Interface............................................................................................................................................................... 40
Loopback Support........................................................................................................................................................... 41
Near-end (Remote) Loopback ........................................................................................................................................ 41
Far-end (Local) Loopback .............................................................................................................................................. 41
CPU Interface I/O Registers ............................................................................................................................................... 42
I/O Registers................................................................................................................................................................... 42
Internal I/O Registers Space Mapping............................................................................................................................ 43
Register Map: MAC, PHY and QMU................................................................................................................................... 49
Bit Type Definition........................................................................................................................................................... 49
0x00 – 0x05: Reserved................................................................................................................................................... 49
Bus Error Status Register (0x06 – 0x07): BESR............................................................................................................ 49
Chip Configuration Register (0x08 – 0x09): CCR .......................................................................................................... 49
0x0A – 0x0F: Reserved .................................................................................................................................................. 50
Host MAC Address Registers: MARL, MARM and MARH ............................................................................................. 50
Host MAC Address Register Low (0x10 – 0x11): MARL................................................................................................ 50
Host MAC Address Register Middle (0x12 – 0x13): MARM........................................................................................... 50
Host MAC Address Register High (0x14 – 0x15): MARH .............................................................................................. 50
0x16 – 0x1F: Reserved .................................................................................................................................................. 51
On-Chip Bus Control Register (0x20 – 0x21): OBCR .................................................................................................... 51
EEPROM Control Register (0x22 – 0x23): EEPCR ....................................................................................................... 51
Memory BIST Info Register (0x24 – 0x25): MBIR .......................................................................................................... 52
Global Reset Register (0x26 – 0x27): GRR ................................................................................................................... 52
0x28 – 0x29: Reserved................................................................................................................................................... 52
Wakeup Frame Control Register (0x2A – 0x2B): WFCR ............................................................................................... 52
0x2C – 0x2F: Reserved .................................................................................................................................................. 53
Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0 ........................................................................................ 53
Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1 ........................................................................................ 53
Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 ................................................................................ 53
Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 ................................................................................ 54
Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 ................................................................................ 54
Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3................................................................................ 54
0x3C – 0x3F: Reserved .................................................................................................................................................. 54
Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0 ........................................................................................ 54
Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1 ........................................................................................ 54
Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 ................................................................................ 54
Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 ................................................................................ 55
Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 ................................................................................ 55
Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3................................................................................ 55
0x4C – 0x4F: Reserved .................................................................................................................................................. 55
Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 ........................................................................................ 55
Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1 ........................................................................................ 55
Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 ................................................................................ 55
August 2009
5 M9999-083109-2.0

5 Page





KSZ8851-32MQLI arduino
Micrel, Inc.
KSZ8851-16/32 MQL/MQLI
Pin Description for 16-Bit
Pin Number
1
Pin Name
TEST_EN
Type
Ipd
2
SCAN_EN
Ipd
3
P1LED2
Opu
4
P1LED1
Ipu/O
Pin Function
Test Enable
For normal operation, open or pull-down this pin to ground.
Scan Test Scan Mux Enable
For normal operation, open or pull-down this pin to ground.
Port 1 LED indicators1 defined as follows:
LED is ON when output is LOW; LED is OFF when output is HIGH.
P1LED32
P1LED2
P1LED1
P1LED0
Chip Global Control Register: CGCR
bit [15,9]
[0,0] Default
[0,1]
——
Link/Act
100Link/Act
Full duplex/Col 10Link/Act
Speed
Full duplex
Reg. CGCR bit [15,9]
P1LED32
[1,0] [1,1]
Act —
5
P1LED0
Ipu/O
P1LED2
P1LED1
Link
Full duplex/Col
P1LED0
Speed
Notes:
1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;
Full Duplex = On (Full duplex); Off (Half duplex)
Speed = On (100BASE-T); Off (10BASE-T)
2. P1LED3 is pin 27.
6 NC — No Connect.
7 NC — No Connect.
8 NC — No Connect.
9
DGND
Gnd Digital ground
10
VDDIO
P 3.3V, 2.5V or 1.8V digital VDDIO input power supply for IO with well decoupling capacitors.
11 NC — No Connect.
12 NC — No Connect.
13 NC — No Connect.
14
PME
Ipu/O Power Management Event: It is asserted (low or high depends on polarity set in PMECR
register) when one of the wake-on-LAN events is detected by KSZ8851M. The
KSZ8851M is requesting the system to wake up from low power mode.
15 NC — No Connect.
16
INTRN
Opu Interrupt
Active Low signal to host CPU to indicate an interrupt status bit is set.
17
LDEVN
Opu Local Device Not
Active Low output signal, asserted when AEN is Low and A7-A1 decode to the
KSZ8851M right address register. LDEVN is a combinational decode of the Address and
AEN signal.
August 2009
11 M9999-083109-2.0

11 Page







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