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Número de pieza | BL55024 | |
Descripción | LCD Driver | |
Fabricantes | BELLING | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de BL55024 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
No Preview Available ! BL55024
Shanghai Belling Corp., Ltd
zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865
LCD Driver for 60 Display Units BL55024
1 General Description
The BL55024 is a general LCD driver IC for 60 units LCD panel. It features a wide
operating supply voltage range, incorporates simple communication interface with
microcomputer and is suitable for multiple application.
2 Features
Advanced low power CMOS Technology
Selection of 1/2 or 1/3 bias, selection of 1/2 or 1/3 or 1/4 duty.
Operation voltage: 2.5~5.5V
Serial data interface
60(15x4) Display Units
Low power dissipation design: Power saving mode: Idd=14uA at 5V and Idd=9uA at
3.3V;
On-chip RC oscillator
VLCD for adjusting LCD operating voltage
Excellent EMC immunity
Compatible with general microcomputer
SOP24 package
3 Pin Assignment
4 Pin Description
Pin No.
1
2
3
4
5
6-9
10-24
Fig 1
Pin name
SDA
SCI
Vdd
Vss
Vlcd
Com0、Com2、Com1、Com3
S0——S14
Tab.1
Function
Serial data input/output
Serial clock input
Supply voltage
ground
LCD supply voltage
Common terminal driving output
Segment terminal driving output
1
1 page BL55024
8 AC Characteristic
Symbol Parameter
Shanghai Belling Corp., Ltd
zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865
Ta=25oC
Test Condition
Min Typ Max Unit
Fclk Oscillator
Vdd=5V,normal mode
125
180
300
KHz
frequency
Fclk Oscillator
Vdd=3.3V, power saving 21 31 48 KHz
frequency
mode
Tclk Half oscillator cycle
1 - 3 uA
Tsh1
CS start hold time
5-
us
Tsh2
tlow
SCL start hold time
High time
5-
5-
us
us
thig Low time
4-
us
thd SCL hold time
250 ns
Fig 6
9 Typical Application Circuit
Note:1/ when I2C are idle mode,SDA and SCL must be connect to high level(by pull up
resistor),otherwise the device maybe can not go into power saving mode.
2/ In power-saving mode, SCL frequency must be less than 21KHz.
3/ Work at 1/3 bias, Vdd – Vlcd must be more than 2.9V。
Fig 7
5
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet BL55024.PDF ] |
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