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PDF FUSB2805 Data sheet ( Hoja de datos )
| Número de pieza | FUSB2805 | |
| Descripción | USB2.0 High-Speed OTG Transceiver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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September 2013
FUSB2805
USB2.0 High-Speed OTG Transceiver with ULPI Interface
Features
Complies with USB 2.0, OTG Rev 1.3 Supplement,
and ULPI Rev 1.1 Specifications
Supports 480 Mbps, 12 Mbps, and 1.5 Mbps
USB2.0 Speeds
- Integrated Termination Resistors Meet USB2.0
Resistor ECN
- Integrated Serializer and Deserializer
- Insertion and Removal of Stuffed Bits
as Appropriate
- USB Clock and Data Recovery to ±150ppm
Supports USB OTG Rev 1.3 Host Negotiation
Protocol (HNP) and Session Request Protocol
(SRP)
15 kV ESD, IEC 61000 Board Level, Air Gap
Applications
Set-Top Box Video Camera, MP3 Player
Cell Phone, Digital Still Camera, PDA
DVD Recorder, Scanner, Printer
Description
The FUSB2805 is a UTMI+ Low-Pin Interface (ULPI)
USB2.0 OTG transceiver. It is compliant with the
Universal Serial Bus Specification Rev 2.0 (USB2.0),
the ULPI Specification Rev. 1.1, and the On-The-Go
(OTG) supplement to USB2.0, Rev. 1.3.
The FUSB2805 is optimized to connect the USB2.0
host, peripheral, or OTG-controller to the USB
connector via the ULPI link. Data can be transmitted
and received at high speed (480 Mbps), full speed
(12 Mbps), and low speed (1.5 Mbps) through a 12-bit
(SDR) interface.
Related Resources
UTMI+ Low Pin Interface Specification (ULPI), Revision
1.1, October 20, 2004. http://www.ulpi.org
UTMI+ Specification, Revision 1.0, February 22, 2004.
http://www.ulpi.org
For additional performance information, please contact
Ordering Information
Part Number
FUSB2805MLX
Top Mark
FUSB2805
Operating Temperature Range
Package
-40 to +85°C
32-Terminal, Molded Leadless
Package (MLP), Quad, JEDEC MO-220
© 2008 Fairchild Semiconductor Corporation
FUSB2805 • Rev. 1.0.3
www.fairchildsemi.com
1 page  
CLOCK
Chip_Select_N
D[7:0] 3-State (input)
STP
3-State (input)
NXT
DIR
tPWRDN
3-State (ignored)
3-State (ignored)
3-State (ignored)
3-State
3-State
Figure 3. ULPI Behavior with Chip_Select_N as a Power-Down Control Signal
Power Down Using Chip_Select
When CHIP SELECT_N is de-asserted (HIGH), the
FUSB2805 three-states the ULPI interface pins and
powers down the internal circuitry. If CHIP
SELECT_N is not used as a power-down control
signal, it is tied to a LOW. Figure 3 shows the ULPI
interface behavior when CHIP SELECT_N is
asserted and subsequently de-asserted.
After the tPWRDN duration, the CLOCK output enters
three-state and is ignored by the link.
Power-On Reset (POR)
The power supply for the internal regulators is VCC. This
supply is fed into the 3.3 V and 1.2 V regulators. The
output of the 3.3 V regulator is VCC3V3. The 1.2 V
regulator generates VDD1V2.
During the power-up stage, the POR is held in a stable
state to ensure that the digital logic does not operate
the I/O or any analog circuit in such a way that may be
damaging to the rest of the system.
The output of the POR block, PORB (internal signal),
should be 1‟b0 during the power supply ramping period.
Once the power supplies have completely ramped,
PORB should be de-asserted. This signal is driven into
the 19.2 / 26 MHz to 12 MHz PLL. The POR signal
(active HIGH reset) in the USB OTG PHY block must
remain asserted for no less than 40 µs.
PORB de-assertion is determined via a comparator on
VCC3V3 with a POR trigger threshold, VPOR, of 2.0 V.
Figure 4 illustrates how PORB should be pulsed based
on the voltage level of VCC3V3. This diagram also shows
what the POR should do to PORB when VCC3V3 drops
below VPOR for any length of time.
When CLOCK starts toggling after power up, the USB
link controller must issue a reset command over the
ULPI bus to ensure correct operation.
PORB /
PLL
Reset
PHY POR
VCC3V3
VPOR
T0 T1
VCC3V3 = 3.3V
VPOR = 2.2V
T1 = T0 + 40µs
T4 = T3 + 40µs
T2 T3 T4
Figure 4. Power-On Reset Sequence
© 2008 Fairchild Semiconductor Corporation
FUSB2805 • Rev. 1.0.3
5
www.fairchildsemi.com
5 Page 
Table 2. Signal Mapping on ULPI Bus During 6-Pin Serial Mode
Signal Maps To Direction
Description
TX_ENABLE
TX_DATA
TX_SE0
INT
RX_DP
RX_DM
RX_RCV
RESERVED
D0
D1
D2
D3
D4
D5
D6
D7
In Active-HIGH transmit enable
In Transmit the differential data on DP and DM
In Transmit single-ended zero (SE0) on DP and DM
Out
Active-HIGH interrupt signal; asserted and latched whenever any
unmasked interrupt occurs
Out Single-ended receive data from DP
Out Single-ended receive data from DM
Out Differential receive data from DP and DM
Out Reserved; the FUSB2805 drives this pin LOW
3-Pin FS/LS Serial Mode
This mode is provided for links that contain legacy
FS/LS functionality and enables a cost-effective
upgrade path to HS functionality.
To enter 3-pin serial mode, the link controller sets the
3PIN_FSLS_SERIAL bit in the interface control register to
logic 1. To exit this mode, the link controller asserts STP.
An INT signal is also provided to inform the link of USB
events. If the link requires CLOCK to be running during 3-
pin serial mode, the CLK_SUSPENDM register bit must
be set to logic 1b before entering 3-pin serial mode.
The FUSB2805 requires CLKIN to be kept running when
in 3-pin mode. In 3-pin serial mode, the data bus
assignments are changed to those described in Table
3. Examples of the signaling of data packets are shown
in Figure 21.
Table 3. Signal Mapping on ULPI Bus During 3-Pin Serial Mode
Signal Maps To Direction
Description
TX_ENABLE
DAT
SE0
INT
RESERVED
D0
D1
D2
D3
D[7:4]
In Active-HIGH transmit enable
I/O
Transmit differential data on DP and DM when TX_ENABLE is HIGH
Receive differential data from DP and DM when TX_ENABLE is LOW
I/O
Transmit single-ended zero on DP and DM when TX_ENABLE is HIGH
Receive single-ended zero on DP and DM when TX_ENABLE is LOW
Out
Active-HIGH interrupt signal; asserted and latched whenever any
unmasked interrupt occurs
Out Reserved; the FUSB2805 drives this pin LOW
Power Supply Modes
The FUSB2805 supports two basic modes of supply
operation and include the following:
Normal Mode
Power-Down Mode
Normal Mode
This mode is entered when VCC and VIO are powered
and Chip_Select_N is asserted.
Power-Down Mode
When chip select is inactive, FUSB2805 enters power-
down mode, during which the following apply:
Chip_Select_N is HIGH or VIO is not present.
All internal circuits are powered down; total VCC
current <36 µA.
D[0-7], CLOCK, NXT, and DIR are three-stated and
ignored; STP is ignored.
Voltage regulators powering the OTG PHY are
turned off.
Pull-down resistors on the ULPI interface are
enabled to prevent a floating bus (VIO present).
The FUSB2805 is forced into a low-power state
and ignores any ULPI commands, including
wake-up events.
If VIO is not present, those signals referenced to VIO
are also not powered.
© 2008 Fairchild Semiconductor Corporation
FUSB2805 • Rev. 1.0.3
11
www.fairchildsemi.com
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| PDF Descargar | [ Datasheet FUSB2805.PDF ] | |
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