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PDF XS1-L8A-64-LQ64 Data sheet ( Hoja de datos )

Número de pieza XS1-L8A-64-LQ64
Descripción xCORE Multicore Microcontrollers
Fabricantes Xmos 
Logotipo Xmos Logotipo



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XS1-L8A-64-LQ64 Datasheet
2015/04/14
XMOS © 2015, All Rights Reserved
Document Number: X4912,

1 page




XS1-L8A-64-LQ64 pdf
XS1-L8A-64-LQ64 Datasheet
4
2 XS1-L8A-64-LQ64 Features
Multicore Microcontroller with Advanced Multi-Core RISC Architecture
Eight real-time logical cores
Core share up to 500 MIPS
Each logical core has:
— Guaranteed throughput of between 1/4 and 1/8 of tile MIPS
— 16x32bit dedicated registers
159 high-density 16/32-bit instructions
— All have single clock-cycle execution (except for divide)
— 32x3264-bit MAC instructions for DSP, arithmetic and user-definable cryptographic
functions
Programmable I/O
36 general-purpose I/O pins, configurable as input or output
— Up to 16 x 1bit port, 5 x 4bit port, 2 x 8bit port, 1 x 16bit port
— 2 xCONNECT links
Port sampling rates of up to 60 MHz with respect to an external clock
32 channel ends for communication with other cores, on or off-chip
Memory
64KB internal single-cycle SRAM for code and data storage
8KB internal OTP for application boot code
Hardware resources
6 clock blocks
10 timers
4 locks
JTAG Module for On-Chip Debug
Security Features
Programming lock disables debug and prevents read-back of memory contents
AES bootloader ensures secrecy of IP held on external flash memory
Ambient Temperature Range
Commercial qualification: 0 °C to 70 °C
Industrial qualification: -40 °C to 85 °C
Speed Grade
5: 500 MIPS
4: 400 MIPS
Power Consumption
Active Mode
— 200 mA at 500 MHz (typical)
— 160 mA at 400 MHz (typical)
Standby Mode
— 14 mA
64-pin LQFP package 0.5 mm pitch
X4912,
XS1-L8A-64-LQ64

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XS1-L8A-64-LQ64 arduino
XS1-L8A-64-LQ64 Datasheet
100MHz
reference
clock
divider
Figure 4:
Clock block
diagram
clock block
... ...
readyIn
port counter
10
1-bit port
X4912,
In many cases I/O signals are accompanied by strobing signals. The xCORE ports
can input and interpret strobe (known as readyIn and readyOut) signals generated
by external sources, and ports can generate strobe signals to accompany output
data.
On reset, each port is connected to clock block 0, which runs from the xCORE Tile
reference clock.
5.5 Channels and Channel Ends
Logical cores communicate using point-to-point connections, formed between two
channel ends. A channel-end is a resource on an xCORE tile, that is allocated by
the program. Each channel-end has a unique system-wide identifier that comprises
a unique number and their tile identifier. Data is transmitted to a channel-end by
an output-instruction; and the other side executes an input-instruction. Data can
be passed synchronously or asynchronously between the channel ends.
5.6 xCONNECT Switch and Links
XMOS devices provide a scalable architecture, where multiple xCORE devices can
be connected together to form one system. Each xCORE device has an xCONNECT
interconnect that provides a communication infrastructure for all tasks that run on
the various xCORE tiles on the system.
The interconnect relies on a collection of switches and XMOS links. Each xCORE
device has an on-chip switch that can set up circuits or route data. The switches
are connected by xConnect Links. An XMOS link provides a physical connection
between two switches. The switch has a routing algorithm that supports many
different topologies, including lines, meshes, trees, and hypercubes.
The links operate in either 2 wires per direction or 5 wires per direction mode,
depending on the amount of bandwidth required. Circuit switched, streaming
and packet switched data can both be supported efficiently. Streams provide the
fastest possible data rates between xCORE Tiles (up to 250 MBit/s), but each stream
requires a single link to be reserved between switches on two tiles. All packet
communications can be multiplexed onto a single link.
XS1-L8A-64-LQ64

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