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PDF LD7520 Data sheet ( Hoja de datos )
| Número de pieza | LD7520 | |
| Descripción | Smart Green-Mode PWM Controller | |
| Fabricantes | Leadtrend Technology | |
| Logotipo |  |
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LD7520
11/29/2007
Smart Green-Mode PWM Controller with Multiple Protections
Spec. 02a
General Description
The LD7520 is a low startup current, current mode PWM
controller with green-mode power-saving operation. The
SOP-8/DIP-8 package integrated functions such as the
leading- edge blanking of the current sensing, internal slope
compensation, line compensation, and several protection
features. The protection functions include cycle-by-cycle
current limit, OVP, OTP, and OLP. It provides the users a
high efficiency, low external component counts solution for
AC/DC power applications.
Furthermore, to satisfy various protection requirements,
both latch-mode protection and auto-recoverable protection
can be easily achieved by configuring LD7520 in different
operation modes.
The special green-mode control is not only to achieve the
low power consumption but also to offer a non-audible-noise
operation when the LD7520 is operating under light load or
no load condition.
Features
z High-Voltage CMOS Process with Excellent ESD
protection
z Very Low Startup Current (< 35μA)
z Current Mode Control
z Non-audible-noise Green Mode Control
z UVLO (Under Voltage Lockout)
z LEB (Leading-Edge Blanking) on CS Pin
z Internal Slope Compensation
z Programmable Line Compensation
z OVP (Over Voltage Protection)
z OLP (Over Load Protection)
z OTP (Over Temperature Protection) through a NTC
z Flexibility on Latch/Auto-Recoverable Protection Mode
z 500mA Driving Capability
Applications
z Switching AC/DC Adaptor and Battery Charger
z Open Frame Switching Power Supply
z LCD Monitor/TV Power
Typical Application
Leadtrend Technology Corporation
LD7520-DS-02a November 2007
1
www.leadtrend.com.tw
1 page  
Electrical Characteristics
(TA = +25oC unless otherwise stated, VCC=15.0V)
PARAMETER
CONDITIONS
Supply Voltage (VCC Pin)
Startup Current
Operating Current
(with 1nF load on OUT pin)
VCOMP=0V
VCOMP=3V
Protection Mode (note 1)
UVLO (off)
UVLO (on)
Voltage Feedback (Comp Pin)
Short Circuit Current
Green Mode Threshold VCOMP
VCOMP=0V
Current Sensing (CS Pin)
Maximum Input Voltage, VCS(OFF)
Leading Edge Blanking Time
VLINE=0V
VLINE=1.25V
VLINE=3.75V
Input impedance
Delay to Output
Gate Drive Output (OUT Pin)
Output Low Level
Output High Level
Rising Time
VCC=15V, Io=20mA
VCC=15V, Io=20mA
Load Capacitance=1000pF
Falling Time
Load Capacitance=1000pF
Oscillator
Frequency
Green Mode Frequency
Frequency Temp. Stability
(-40°C –85°C)
Frequency Voltage Stability
(VCC=12V-30V)
Latch Protection ((-)LATCH Pin)
(-)LATCH Pin Source Current
Turn-On Trip Level
Turn-Off Trip Level
(-)LATCH pin de-bounce time
De-latch Vcc Level
(PDR, Power Down Reset)
Note 1: When OVP, OLP, or Latch Protection is tripped.
LD7520
MIN
TYP
MAX UNITS
20 35 μA
3.5 5.0 mA
3.0 mA
0.7 mA
9.0
10.0
11.0
V
15.0
16.0
17.0
V
2.5
2.35
4.0 mA
V
0.800
0.750
0.650
1
0.850
0.800
0.700
350
150
0.900
0.850
0.750
V
V
V
nS
MΩ
nS
1.0 V
9.0 V
50 160 nS
30 60 nS
60 65 70 KHz
20 KHz
3%
1%
92 100 108 μA
3.3
3.50
3.7
V
2.40
2.50
2.60
V
100 μS
6.8 8.0 8.7 V
Leadtrend Technology Corporation
LD7520-DS-02a November 2007
5
www.leadtrend.com.tw
5 Page 
LD7520
pin of LD7520. The input stage of LD7520, like the
UC384X, is with 2 diodes voltage offset then feeding into the
voltage divider with 1/3 ratio, that is,
V+ (PWM COMPARATOR
)
=
1
3
× (VCOMP
−
2VF )
A pull-high resistor is embedded internally thus can be
eliminated on the external circuit.
A 350nS leading-edge blanking (LEB) time is included in the
input of CS pin to prevent the false-trigger from the current
spike. However, the total pulse width of the turn-on spike is
decided by the output power, circuit design and PCB layout.
It is strongly recommended to adopt a smaller R-C filter (as
shown in figure 19) to avoid the CS pin being damaged by
the negative turn-on spike.
Dual-Oscillator Green-Mode Operation
There are many different topologies has been implemented
in different chips for the green-mode or power saving
requirements such as “burst-mode control”, “skipping-cycle
mode”, “variable off-time control “…etc. The basic operation
theory of all these approaches intended to reduce the
switching cycles under light-load or no-load condition either
by skipping some switching pulses or reduce the switching
frequency.
By using this dual-oscillator control, the green-mode
frequency can be well controlled and further to avoid the
generation of audible noise.
Internal Slope Compensation
A fundamental issue of current mode control is the stability
problem when its duty-cycle is operated more than 50%. To
stabilize the control loop, the slope compensation is needed
in the traditional UC384X design by injecting the ramp signal
from the RT/CT pin through a coupling capacitor. In LD7520,
the internal slope compensation circuit has been
implemented to simplify the external circuit design.
Current Sensing, Leading-Edge Blanking
The typical current mode PWM controller feedbacks both
current signal and voltage signal to close the control loop
and achieve regulation. The LD7520 detects the primary
MOSFET current from the CS pin, which is not only for the
peak current mode control but also for the pulse-by-pulse
current limit. The maximum voltage threshold of the current
sensing pin is set as 0.85V. Thus the MOSFET peak current
can be calculated as:
IPeak(Max.)
=
(0.85
−
Vline _ compensation )
RS
Fig. 19
Adjustable Line Compensation
As all the users of UC384X well know, it is usually need the
extra line compensation circuit which must be connected
from bulk voltage to the CS pin to compensate the OCP trip
level difference. However, the CS pin is a node with
switching signal and is sensitive so that the external resistor
value can’t be very high. Thus the generated power losses
on the external resistors for line compensation will be
significant. To get the trade-off between the OCP
performance and the reduction on the power losses,
LD7520 provides a high input impedance pin for the
programming of line compensation. Figure 20 shows the
line compensation circuit in LD7520.
Due to the CMOS process, the input impedance of LINE pin
can be very high, therefore the resistor of R1 can be as high
as 10M Ohm. By adjusting the value of R1, R2 and current
sense resistor, the OCP level of high-line and low-line can
be set to very closed values.
Leadtrend Technology Corporation
LD7520-DS-02a November 2007
11
www.leadtrend.com.tw
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet LD7520.PDF ] | |
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