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PDF LD7532H Data sheet ( Hoja de datos )
| Número de pieza | LD7532H | |
| Descripción | Green-Mode PWM Controller | |
| Fabricantes | Leadtrend Technology | |
| Logotipo |  |
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LD7532H
12/17/2008
Green-Mode PWM Controller with
OLP/ OVP Latch off Protections
REV: 00
General Description
The LD7532H is specifically designed for low cost
total-system by integrating many functions, protections,
and EMI-improved solution in a SOT-26 package, which
usually needs a lot of extra components or circuits on
general system designs.
Furthermore, the CT pin latch function by injecting a high
above 3.1V provides power circuit designers an easy way
to deal with designs for protections, such as OVP and
OTP, minimizing component cost and development time.
In order to satisfy different designs, the OVP trig level is
adjustable by users adding a Zener diode from VCC pin to
CT pin.
Typical Application
Features
z High-Voltage CMOS Process with ESD protection
z Very Low Startup Current (<20μA)
z Current Mode Control
z Non-audible-noise Green Mode Control
z UVLO (Under Voltage Lockout) on VCC Pin
z LEB (Leading-Edge Blanking) on CS Pin
z Programmable OLP Delay Time
z Internal Slope Compensation
z External OVP Latch-off Protection
z OLP (Over Load Protection) Latch-off Mode
z External OTP Latch-off Protection
z 300mA Driving Capability
Applications
z Switching AC/DC Adaptor and Battery Charger
z Open Frame Switching Power Supply
AC EMI
input Filter
OUT
NTC
CT
COMP
VCC
32V
16.0V
/9.0V
LD7532H
OSC
Divider
UVLO
Control
Logic
GND
OUT
CS
Leadtrend Technology Corporation
LD7532H-DS-00 December 2008
1
www.leadtrend.com.tw
photocoupler
TL431
1 page  
LD7532H
Electrical Characteristics
(TA = +25oC unless otherwise stated, VCC=15.0V)
PARAMETER
CONDITIONS
Supply Voltage (Vcc Pin)
Startup Current
Operating Current
(with 1nF load on OUT pin)
UVLO (off)
VCOMP=0V
VCOMP=3V
IOLP, OLP Tripped/ Latch
IOVP, CT pin OVP Tripped/ Latch
UVLO (on)
Voltage Feedback (Comp Pin)
Short Circuit Current
Open Loop Voltage
VCOMP=0V
COMP pin open
OLP Current
COMP pin open
Green Mode Threshold VCOMP
Burst Mode Threshold VCOMP
Current Sensing (CS Pin)
Maximum Input Voltage, Vcs(off)
Leading Edge Blanking Time
Input impedance
Delay to Output
Oscillator for Switching Frequency
Frequency
Trembling Range
Green Mode Frequency
Temp. Stability
Voltage Stability
(-40°C ~105°C)
(VCC=11V-25V)
FM Oscillator (CT pin)
Timer Frequency
OVP trigger level (Latch)
CT=0.047μF
Holding Current
Vcc=7V (latched),
Gate Drive Output (OUT Pin)
Output Low Level
VCC=15V, Io=20mA
Output High Level
VCC=15V, Io=20mA
Rising Time
Falling Time
Load Capacitance=1000pF
Load Capacitance=1000pF
Max. Duty
Load Capacitance=1000pF
MIN
9.0
15.0
0.80
1
60
2.9
8
TYP
12
2.5
3.0
1.0
1.0
10.0
16.0
1.5
6.0
1.0
2.35
1.6
0.85
220
100
65
± 3.5
20.5
5
1
220
3.1
250
180
50
75
MAX UNITS
20 μA
mA
mA
mA
mA
11.0 V
17.0 V
mA
V
mA
V
V
0.90 V
nS
MΩ
nS
70 KHz
KHz
KHz
%
%
Hz
3.3 V
μA
1.0 V
V
360 nS
100 nS
%
Leadtrend Technology Corporation
LD7532H-DS-00 December 2008
5
www.leadtrend.com.tw
5 Page 
LD7532H
no-load conditions either by skipping some switching
pulses or reducing the switching frequency.
By using this dual-oscillator control, the green-mode
frequency can be well controlled to further avoid the
generation of audible noise.
Latch Off Control
The LD7532H can be latched off by injecting the CT pin a
voltage signal higher than 3.1V. The gate output pin of the
LD7532H will be disabled immediately under such
condition. The off-mode can’t be released unless the VCC
goes under a de-latch level by recycled the input power.
OVP/OTP Implementation on CT Pin
The OVP function is implemented by adding a Zener
diode from VCC pin to CT pin. The protection is a latch
type. If the OVP condition occurs, usually caused by the
feedback loop opened, the Vcc will trip up to the OVP
level (Vz+3.1V) and shutdown the output. The Vcc will be
discharged to a low level for easily resetting. The figure 18
shows its operation.
The OTP function could be implemented by CT PIN
connected a simple voltage-divider circuit composed with
a proper N.T.C. thermistor connected from OUT pin to this
pin. While temperature is rising and causing the
resistance down, the CT pin voltage will rise to trigger the
IC into latch mode. It could be released by recycling the
input power the same as the OVP behavior.
VCC
OVP Level
UVLO (ON)
UVLO
(OFF)
OUT
OVP Tripped
AC OFF
t
switching
Latch Mode
Fig. 18
D-Latch
t
Over Load Protection (OLP)/ Latch Mode
To protect circuits from being damaged under over load
condition or short condition, a smart OLP function is
implemented in the LD7532H. The figure 19 shows the
waveforms of the OLP operation. In this case, the
feedback system will force the voltage loop proceeding
toward the saturation and then pull up the voltage on
COMP pin (VCOMP). Whenever the VCOMP trips up to the
OLP threshold 5V and stays longer than the OLP delay
time, the protection will be activated to turn off the gate
output and stop the switching of power circuit. The OLP
delay time, set by CT pin, is to prevent any false trigger
caused by the power-on and turn-off transient. The Higher
the CT value is, the longer the OLP delay time. For
recommendation, the OLP delay time is around 95mS
when CT=0.1μF and will be around 45mS when
CT=0.047μF.
As soon as the OLP is tripped, the controller will latch off
until AC power is removed.
Leadtrend Technology Corporation
LD7532H-DS-00 December 2008
11
www.leadtrend.com.tw
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet LD7532H.PDF ] | |
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