PDF EN25QH256 Data sheet ( Hoja de datos )

Número de pieza	EN25QH256
Descripción	256 Megabit Serial Flash Memory
Fabricantes	Eon Silicon Solution
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EN25QH256 EN25QH256 256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector FEATURES • Single power supply operation - Full voltage range: 2.7-3.6 volt • Serial Interface Architecture - SPI Compatible: Mode 0 and Mode 3 • 256 M-bit Serial Flash - 256 M-bit/32,768 K-byte/131,072 pages - 256 bytes per programmable page • Standard, Dual or Quad SPI - Standard SPI: CLK, CS#, DI, DO, WP#, HOLD# - Dual SPI: CLK, CS#, DQ0, DQ1, WP#, HOLD# - Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3 • High performance - 80MHz clock rate for Standard SPI - 80MHz clock rate for two data bits - 50MHz clock rate for four data bits • Low power consumption - 12 mA typical active current - 1 μA typical power down current • Uniform Sector Architecture: - 8192 sectors of 4-Kbyte - 512 blocks of 64-Kbyte - Any sector or block can be erased individually • Software and Hardware Write Protection: - Write Protect all or portion of memory via software - Enable/Disable protection with WP# pin • High performance program/erase speed - Page program time: 0.8ms typical - Sector erase time: 50ms typical - Block erase time 400ms typical - Chip erase time: 100 seconds typical • Lockable 512 byte OTP security sector • Support Serial Flash Discoverable Parameters (SFDP) signature • Read Unique ID Number • Support High Bank Latch Mode • Minimum 100K endurance cycle • Package Options - 8 contact VDFN (6x8mm) - 16 pins SOP 300mil body width - 24 balls BGA (6x8mm) - All Pb-free packages are RoHS compliant • Industrial temperature Range GENERAL DESCRIPTION The EN25QH256 is a 256 Megabit (32,768 K-byte) Serial Flash memory, with enhanced write protection mechanisms. The EN25QH256 supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O using SPI pins: Serial Clock, Chip Select, Serial DQ0(DI), DQ1(DO), DQ2(WP#) and DQ3(HOLD#). SPI clock frequencies of up to 80MHz are supported allowing equivalent clock rates of 160MHz (80MHz x 2) for Dual Output when using the Dual Output Fast Read instructions, and SPI clock frequencies of up to 50MHz are supported allowing equivalent clock rates of 200MHz (50MHz x 4) for Quad Output when using the Quad Output Fast Read instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The EN25QH256 is designed to allow either single Sector/Block at a time or full chip erase operation. The EN25QH256 can be configured to protect part of the memory as the software protected mode. The device can sustain a minimum of 100K program/erase cycles on each sector or block. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 1 ©2004 Eon Silicon Solution, Inc., Rev. F, Issue Date: 2012/06/01 www.eonssi.com 1 page Table 1. Pin Names EN25QH256 Symbol CLK DI (DQ0) DO (DQ1) CS# WP# (DQ2) HOLD# (DQ3) Vcc Vss NC Pin Name Serial Clock Input Serial Data Input (Data Input Output 0) 1 Serial Data Output (Data Input Output 1) 1 Chip Select Write Protect (Data Input Output 2) 2 HOLD# pin (Data Input Output 3) 2 Supply Voltage (2.7-3.6V) Ground No Connect Note: 1. DQ0 and DQ1 are used for Dual and Quad instructions. 2. DQ2 ~ DQ3 are used for Quad instructions. SIGNAL DESCRIPTION Serial Data Input, Output and IOs (DI, DO and DQ0, DQ1, DQ2, DQ3) The EN25QH256 support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge CLK. Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Mode") Chip Select (CS#) The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2 and DQ3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. When CS# is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new instruction will be accepted. Hold (HOLD#) The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same SPI signals. The HOLD# function is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial Data IO (DQ3) for Quad I/O operation. Write Protect (WP#) The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (BP0, BP1, BP2 and BP3) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial Data IO (DQ2) for Quad I/O operation. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 5 ©2004 Eon Silicon Solution, Inc., Rev. F, Issue Date: 2012/06/01 www.eonssi.com 5 Page Table 2. Uniform Block Sector Architecture ( 5/8 ) Block 255 254 253 Sector 4095 4080 4079 4064 4063 4048 Address range 0FFF000h 0FFFFFFh 0FF0000h 0FF0FFFh 0FEF000h 0FEFFFFh 0FE0000h 0FE0FFFh 0FDF000h 0FDFFFFh 0FD0000h 0FD0FFFh Block 239 238 237 EN25QH256 Sector 3839 3824 3823 3808 3807 3792 Address range 0EFF000h 0EFFFFFh 0EF0000h 0EF0FFFh 0EEF000h 0EEFFFFh 0EE0000h 0EE0FFFh 0EDF000h 0EDFFFFh 0ED0000h 0ED0FFFh 3887 0F2F000h 0F2FFFFh 242 3872 0F20000h 0F20FFFh 3871 0F1F000h 0F1FFFFh 241 3856 0F10000h 0F10FFFh 3855 0F0F000h 0F0FFFFh 240 3840 0F00000h 0F00FFFh Block 223 222 221 Sector 3583 Address range 0DFF000h 0DFFFFFh 3568 3567 0DF0000h 0DF0FFFh 0DEF000h 0DEFFFFh 3552 3551 0DE0000h 0DE0FFFh 0DDF000h 0DDFFFFh 3536 0DD0000h 0DD0FFFh 3631 0E2F000h 0E2FFFFh 226 3616 0E20000h 0E20FFFh 3615 0E1F000h 0E1FFFFh 225 3600 0E10000h 0E10FFFh 3599 0E0F000h 0E0FFFFh 224 3584 0E00000h 0E00FFFh Block 207 206 205 Sector 3327 Address range 0CFF000h 0CFFFFFh 3312 3311 0CF0000h 0CF0FFFh 0CEF000h 0CEFFFFh 3296 3295 0CE0000h 0CE0FFFh 0CDF000h 0CDFFFFh 3280 0CD0000h 0CD0FFFh 3375 0D2F000h 0D2FFFFh 210 3360 0D20000h 0D20FFFh 3359 0D1F000h 0D1FFFFh 209 3344 0D10000h 0D10FFFh 3343 0D0F000h 0D0FFFFh 208 3328 0D00000h 0D00FFFh 3119 0C2F000h 0C2FFFFh 194 3014 0C20000h 0C20FFFh 3103 0C1F000h 0C1FFFFh 193 3088 0C10000h 0C10FFFh 3087 0C0F000h 0C0FFFFh 192 3072 0C00000h 0C00FFFh This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 11 ©2004 Eon Silicon Solution, Inc., Rev. F, Issue Date: 2012/06/01 www.eonssi.com 11 Page

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