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PDF ADSP-21488 Data sheet ( Hoja de datos )

Número de pieza ADSP-21488
Descripción SHARC Processor
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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SHARC Processor
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip
ROM
Up to 450 MHz operating frequency
Code compatible with all other members of the SHARC family
The ADSP-2148x processors are available with unique audio-
centric peripherals, such as the digital applications
interface, serial ports, precision clock generators, S/PDIF
transceiver, asynchronous sample rate converters, input
data port, and more
For complete ordering information, see Ordering Guide on
Page 66
Qualified for automotive applications
SIMD Core
Instruction
Cache
5 Stage
Sequencer
DAG1/2
Core
Timer
PEx PEy
FLAGx/IRQx/
TMREXP
JTAG THERMAL
DIODE
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
DMD
64-BIT
S
DMD
64-BIT
Core Bus
PMD
64-BIT
Cross Bar
PMD 64-BIT
EPD BUS 64-BIT
PERIPHERAL BUS
32-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
Internal Memory I/F
IOD0 32-BIT
B3D
64-BIT
IOD1
32-BIT
PERIPHERAL BUS
CORE
FLAGS/
PWM3-1
PCG
C-D
TIMER
1-0
TWI
SPI/B UART
IOD0 BUS
S/PDIF PCG
Tx/Rx A-D
ASRC PDAP/ SPORT
3-0 IDP 7-0
7-0
FFT
FIR
IIR
DTCP/
MTM
SPEP BUS
CORE PWM
WDT FLAGS 3-0
EP
AMI
SDRAM
CTL
DPI Routing/Pins
DPI Peripherals
DAI Routing/Pins
DAI Peripherals
Figure 1. Functional Block Diagram
External Port Pin MUX
Peripherals
External
Port
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

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ADSP-21488 pdf
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
S
SIMD Core
DMD/PMD 64
DAG1
16x32
DAG2
16x32
JTAG FLAG TIMER INTERRUPT CACHE
5 STAGE
PROGRAM SEQUENCER
PM ADDRESS 24
PM DATA 48
PM ADDRESS 32
DM ADDRESS 32
PM DATA 64
DM DATA 64
SYSTEM
I/F
USTAT
4x32-BIT
PX
64-BIT
MULTIPLIER SHIFTER ALU
RF
Rx/Fx
PEx
16x40-BIT
DATA
SWAP
RF
Sx/SFx
PEy
16x40-BIT
ALU
SHIFTER MULTIPLIER
MRF
80-BIT
MRB
80-BIT
ASTATx
STYKx
ASTATy
STYKy
MSB
80-BIT
MSF
80-BIT
Figure 2. SHARC Core Block Diagram
Universal Registers
These registers can be used for general-purpose tasks. The
USTAT (4) registers allow easy bit manipulations (Set, Clear,
Toggle, Test, XOR) for all peripheral registers (control/status).
The data bus exchange register (PX) permits data to be passed
between the 64-bit PM data bus and the 64-bit DM data bus, or
between the 40-bit register file and the PM/DM data bus. These
registers contain hardware to handle the data width difference.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-2148x features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data.
With the its separate program and data memory buses and on-
chip instruction cache, the processor can simultaneously fetch
four operands (two over each data bus) and one instruction
(from the cache), all in a single cycle.
Instruction Cache
The processor includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators With Zero-Overhead Hardware
Circular Buffer Support
The two data address generators (DAGs) are used for indirect
addressing and implementing circular data buffers in hardware.
Circular buffers allow efficient programming of delay lines and
other data structures required in digital signal processing, and
are commonly used in digital filters and Fourier transforms.
The two DAGs contain sufficient registers to allow the creation
of up to 32 circular buffers (16 primary register sets, 16 second-
ary). The DAGs automatically handle address pointer
wraparound, reduce overhead, increase performance, and sim-
plify implementation. Circular buffers can start and end at any
memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
processor can conditionally execute a multiply, an add, and a
Rev. C | Page 5 of 68 | June 2015

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ADSP-21488 arduino
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Delay Line DMA
The processor provides delay line DMA functionality. This
allows processor reads and writes to external delay line buffers
(and hence to external memory) with limited core interaction.
Scatter/Gather DMA
The processor provides scatter/gather DMA functionality. This
allows processor DMA reads/writes to/from non contiguous
memory blocks.
FFT Accelerator
The FFT accelerator implements a radix-2 complex/real input,
complex output FFT with no core intervention. The FFT accel-
erator runs at the peripheral clock frequency.
FIR Accelerator
The FIR (finite impulse response) accelerator consists of a 1024
word coefficient memory, a 1024 word deep delay line for the
data, and four MAC units. A controller manages the accelerator.
The FIR accelerator runs at the peripheral clock frequency.
IIR Accelerator
The IIR (infinite impulse response) accelerator consists of a
1440 word coefficient memory for storage of biquad coeffi-
cients, a data memory for storing the intermediate data, and one
MAC unit. A controller manages the accelerator. The IIR accel-
erator runs at the peripheral clock frequency.
Watchdog Timer
The watchdog timer is used to supervise the stability of the sys-
tem software. When used in this way, software reloads the
watchdog timer in a regular manner so that the downward
counting timer never expires. An expiring timer then indicates
that system software might be out of control.
The 32-bit watchdog timer that can be used to implement a soft-
ware watchdog function. A software watchdog can improve
system reliability by forcing the processor to a known state
through generation of a system reset, if the timer expires before
being reloaded by software. Software initializes the count value
of the timer, and then enables the timer. The watchdog timer
resets both the core and the internal peripherals. Note that this
feature is available on the 176-lead package only.
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues.
Program Booting
The internal memory of the ADSP-2148x boots at system
power-up from an 8-bit EPROM via the external port, an SPI
master, or an SPI slave. Booting is determined by the boot con-
figuration (BOOT_CFG2–0) pins in Table 9 for the 176-lead
package and Table 10 for the 100-lead package.
Table 9. Boot Mode Selection, 176-Lead Package
BOOT_CFG2–0
000
001
010
011
1xx
Booting Mode
SPI Slave Boot
SPI Master Boot
AMI User Boot (for 8-bit Flash Boot)
No boot (processor executes from internal
ROM after reset)
Reserved
Table 10. Boot Mode Selection, 100-Lead Package
BOOT_CFG1–0
00
01
10
11
Booting Mode
SPI Slave Boot
SPI Master Boot
Reserved
No boot (processor executes from internal
ROM after reset)
The “Running Reset” feature allows a user to perform a reset of
the processor core and peripherals, but without resetting the
PLL and SDRAM controller, or performing a boot. The
functionality of the RESETOUT/RUNRSTIN pin has now been
extended to also act as the input for initiating a Running Reset.
For more information, see the ADSP-214xx SHARC Processor
Hardware Reference.
Power Supplies
The processors have separate power supply connections for the
internal (VDD_INT) and external (VDD_EXT) power supplies. The
internal supply must meet the VDD_INT specifications. The
external supply must meet the VDD_EXT specification. All exter-
nal supply pins must be connected to the same power supply.
To reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for VDD_INT and GND.
Static Voltage Scaling (SVS)
Some models of the ADSP-2148x feature Static Voltage Scaling
(SVS) on the VDD_INT power supply. (See the Ordering Guide
on Page 66 for model details.) This voltage specification tech-
nique can provide significant performance benefits including
450 MHz core frequency operation without a significant
increase in power.
SVS optimizes the required VDD_INT voltage for each individual
device to enable enhanced operating frequency up to 450 MHz.
The optimized SVS voltage results in a reduction of maximum
IDD_INT which enables 450 MHz operation at the same or lower
maximum power than 400 MHz operation at a fixed voltage
supply. Implementation of SVS requires a specific voltage regu-
lator circuit design and initialization code.
Refer to the Engineer-to-Engineer Note “Static Voltage Scaling
for ADSP-2148x Processors” (EE-357) for further information.
The EE-Note details the requirements and process to implement
a SVS power supply system to enable operation up to 450 MHz.
This applies only to specific products within the ADSP-2148x
family which are capable of supporting 450 MHz operation.
Rev. C | Page 11 of 68 | June 2015

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