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PDF SC16C2550B Data sheet ( Hoja de datos )
| Número de pieza | SC16C2550B | |
| Descripción | dual UART | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte
FIFOs
Rev. 05 — 12 January 2009
Product data sheet
1. General description
The SC16C2550B is a two channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert parallel
data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.
The SC16C2550B is pin compatible with the ST16C2550. It will power-up to be
functionally equivalent to the 16C2450. The SC16C2550B provides enhanced UART
functions with 16-byte FIFOs, modem control interface, DMA mode data transfer. The
DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDYn and
RXRDYn signals. On-board status registers provide the user with error indications and
operational status. System interrupts and modem control features may be tailored by
software to meet specific user requirements. An internal loopback capability allows
on-board diagnostics. Independent programmable baud rate generators are provided to
select transmit and receive baud rates.
The SC16C2550B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,
and is available in plastic PLCC44, LQFP48, DIP40 and HVQFN32 packages.
2. Features
I 2 channel UART
I 5 V, 3.3 V and 2.5 V operation
I 5 V tolerant on input only pins1
I Industrial temperature range
I Pin and functionally compatible to 16C2450 and software compatible with INS8250,
SC16C550
I Up to 5 Mbit/s data rate at 5 V and 3.3 V and 3 Mbit/s at 2.5 V
I 16-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
I 16-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
I Independent transmit and receive UART control
I Four selectable Receive FIFO interrupt trigger levels
I Software selectable baud rate generator
I Standard asynchronous error and framing bits (Start, Stop and Parity Overrun Break)
I Transmit, Receive, Line Status and Data Set interrupts independently controlled
1. For data bus pins D7 to D0, see Table 23 “Limiting values”.
1 page  
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
D5 7
D6 8
D7 9
RXB 10
RXA 11
TXRDYB 12
TXA 13
TXB 14
OP2B 15
CSA 16
CSB 17
SC16C2550BIA44
39 RESET
38 DTRB
37 DTRA
36 RTSA
35 OP2A
34 RXRDYA
33 INTA
32 INTB
31 A0
30 A1
29 A2
002aaa597
Fig 4. Pin configuration for PLCC44
D5 1
D6 2
D7 3
RXB 4
RXA 5
TXRDYB 6
TXA 7
TXB 8
OP2B 9
CSA 10
CSB 11
n.c. 12
SC16C2550BIB48
Fig 5. Pin configuration for LQFP48
36 RESET
35 DTRB
34 DTRA
33 RTSA
32 OP2A
31 RXRDYA
30 INTA
29 INTB
28 A0
27 A1
26 A2
25 n.c.
002aaa598
SC16C2550B_5
Product data sheet
Rev. 05 — 12 January 2009
© NXP B.V. 2009. All rights reserved.
5 of 43
5 Page 
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.3 FIFO operation
The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
(FCR) bit 0. The user can set the receive trigger level via FCR bits 7:6, but not the transmit
trigger level. The receiver FIFO section includes a time-out function to ensure data is
delivered to the external CPU. An interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the loading of a character or the receive
trigger level has not been reached.
Table 6. Flow control mechanism
Selected trigger level (characters)
1
4
8
14
INTn pin activation
1
4
8
14
6.4 Hardware/software and time-out interrupts
The interrupts are enabled by IER[3:0]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C2550B
will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to
continuing operations. The ISR register provides the current singular highest priority
interrupt only. A condition can exist where a higher priority interrupt may mask the lower
priority interrupt(s). Only after servicing the higher pending interrupt will the lower priority
interrupt(s) be reflected in the status register. Servicing the interrupt without investigating
further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C2550B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive Time
Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center
of each stop bit received or each time the Receive Holding Register (RHR) is read. The
actual time-out value is 4 character time, including data information length, start bit, parity
bit and the size of stop bit, that is, 1×, 1.5× or 2× bit times.
SC16C2550B_5
Product data sheet
Rev. 05 — 12 January 2009
© NXP B.V. 2009. All rights reserved.
11 of 43
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