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PDF IDT74ALVC1G32 Data sheet ( Hoja de datos )
| Número de pieza | IDT74ALVC1G32 | |
| Descripción | 3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE | |
| Fabricantes | IDT | |
| Logotipo |  |
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IDT74ALVC1G32
3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS
SINGLE 2-INPUT
POSITIVE-OR GATE
IDT74ALVC1G32
FEATURES:
– 0.5 MICRON CMOS Technology
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.65mm pitch PSOP package
– Extended commercial range of – 40°C to + 85°C
– VCC = 3.3V ± 0.3V, Normal Range
– VCC = 1.65V to 3.6V, Extended Range
– VCC = 2.5V ± 0.2V
– CMOS power levels (0.4µ W typ. static)
– Rail-to-Rail output swing for increased noise margin
Drive Features for ALVC1G32:
– High Output Drivers: ±24mA
– Suitable for heavy loads
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
This single 2-input positive-OR gate is built using advanced dual
metal CMOS technology. The ALVC1G32 is designed for 1.65V to
3.6V VCC operation and performs the Boolean function Y = A + B or Y
= A • B in positive logic.
The ALVC1G32 has been designed with a ±24mA output driver.
This driver is capable of driving a moderate to heavy load while
maintaining speed performance.
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
PIN CONFIGURATION
A1
2
B
A1
5 VCC
4 Y B 2 SO5-1
GND
3
4Y
PSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
A, B Data Inputs
Y Data Output
Description
FUNCTION TABLE (1)
Inputs
AB
HX
XH
LL
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
Output
Y
H
H
L
EXTENDED COMMERCIAL TEMPERATURE RANGE
c 1999 Integrated Device Technology, Inc.
1
FEBRUARY 2000
DSC-4532/-
1 page  
IDT74ALVC1G32
3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
1.8V ± 0.15V TEST CIRCUITS AND WAVEFORMS:
TEST CONDITIONS
Symbol
VCC(1)= 1.8V ± 0.15V
VLOAD
2 x VCC
VIH VCC
VT VCC / 2
PROPAGATION DELAY
Unit
V SAME PHASE
INPUT TRANSITION
V
tPLH
tPHL
OUTPUT
V
VLZ 150 mV
tPLH
tPHL
VHZ 150 mV O PPO SITE PHASE
CL 30 pF INPU T TRANSITIO N
ALVC 1G Link
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
ALVC 1G Link
TEST CIRCUITS FOR ALL OUTPUTS
VCC
VLOAD
Open
P u ls e(1 )
G ene rato r
V IN
VOUT
D.U.T.
1000Ω GND
RT
1000Ω
CL
DEFINITIONS:
ALVC 1G Link
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTE:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
ENABLE AND DISABLE TIMES
CONTROL
IN P U T
ENABLE
tPZL
D IS A B L E
tPLZ
V IH
VT
0V
OUTPUT SWITCH
NORMALLY CLOSED
LOW
tPZH
OUTPUT
S W IT C H
NORMALLY
OPEN
H IG H
VLOAD/2
VT
tPHZ
VT
0V
VLOAD/2
VLZ
VOL
VOH
VHZ
0V
ALVC 1G Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
PULSE WIDTH
Switch
VLOAD
GND
Open
DATA
IN P U T
T IM IN G
IN P U T
ALVC 1G Link
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU tH
tREM
tSU tH
V IH
VT
0V
V IH
VT
0V
V IH
VT
0V
V IH
VT
0V
ALVC 1G Link
LO W -H IG H -LO W
PULSE
H IG H -LO W -H IG H
PULSE
VT
tW
VT
ALVC 1G Link
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT74ALVC1G32.PDF ] | |
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