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PDF TS25L16APP Data sheet ( Hoja de datos )

Número de pieza TS25L16APP
Descripción 16 Mbit Serial Flash memory
Fabricantes Terra Semiconductor 
Logotipo Terra Semiconductor Logotipo



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TS25L16APP
16 Mbit Serial Flash memory with 75 MHz
Dual and Quad SPI bus Interface
Features
Architectural Advantages
n Single power supply operation
• Full voltage range: 2.7 to 3.6 V read and
program operations
n Memory Architecture
• 32ea sectors with 512 Kb each
n Program
• Page Program (up to 256 bytes) in 0.3 ms
(typical)
• Page Write (up to 256 bytes) in 2.8 ms
(typical)
• Program cycles are on a page by page basis
n Erase
• 2ms typical Page Erase Time
• 2ms typical SubSector Erase Time
• 32ms typical Sector Erase time
• 1 sec typical Bulk Erase time
n Cycling Endurance
• 100,000 P/E cycles per sector typical
n Data Retention
• 20 years typical
n Device ID
• JEDEC standard two-byte electronic
signature
n Package Option
• Industry Standard Pin-outs
• 8-pin SOP 208 mil
• 8-pin SOP 150 mil
• 8-pin PDIP 300 mil
Performance Characteristics
n Speed
• 75 MHz clock rate (maximum)
n Dual/Quad Output Speed
• 150 MHz/300 MHz an equivalent clock rate
(maximum)
n Power Saving Standby Mode
• Standby Mode 1 µA (typical)
• Deep Power-down Mode 1 µA (typical)
Memory Protection Features
n Memory Protection
• W# (SO2) pin works in conjunction with
Status Register Bits to protect specified
memory areas
• Status Register Block Protection bits (BP3,
BP2, BP1, BP0) in status register configure
parts of memory as read-only
Software Features
n SPI Bus Compatible Serial Interface
May 2009
1/1 Terra Semiconductor

1 page




TS25L16APP pdf
List of figures
TS25L16APP
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Figure 33.
Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
SOP 8pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus Master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI modes supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . 22
Read Status Register(RDSR) instruction sequence and data-out sequence . . . . . . . . . . 24
Write Status Register(WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 27
Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Fast Read Dual Output (FRDO) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Fast Read Quad Output (FRQO) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . 32
Page Write (PW) instruction sequence . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Page Erase (PE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SubSector Erase (SSE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Release from Deep Power-down (RES) instruction sequence . . . . . . . . . . . . . . . . . . . .39
Release from Deep Power-down and Read Electronic Signature (RES) instruction
sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Write Protect setup and hold timing during WRSR when SRWD = 1. . . . . . . . . . . . . . . . . 47
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SOP – 8 lead Plastic Small Outline, 208 mils body width, package outline . . . . . . . . 49
SOP – 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . . . . . . 50
PDIP – 8 lead Plastic Small Outline, 300 mils body width, package outline . . . . . . . . . . . 51
May 2009
5/5 Terra Semiconductor

5 Page





TS25L16APP arduino
Figure 4. SPI modes supported
CPOL CPHA
0 0 SCK
1 1 SCK
SI MSB
SO
TS25L16APP
MSB
May 2009
11/11
Terra Semiconductor

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