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PDF W25D80 Data sheet ( Hoja de datos )
| Número de pieza | W25D80 | |
| Descripción | SERIAL FLASH MEMORY | |
| Fabricantes | Winbond | |
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W25D10, W25D20, W25D40, W25D80
1M-BIT, 2M-BIT, 4M-BIT AND 8M-BIT
SERIAL FLASH MEMORY WITH
4KB SECTORS AND DUAL OUTPUT SPI
Publication Release Date: July 15, 2006
- 1 - Preliminary - Revision A
1 page  
W25D10, W25D20, W25D40, W25D80
3. PIN CONFIGURATION SOIC 150-MIL
Figure 1a. W25D10, W25D20 and W25D40 Pin Assignments, 8-pin SOIC (Package Code SN)
4. PIN CONFIGURATION SOIC 208-MIL
Figure 1b。W25D40 and W25D80 Pin Assignments, 8-pin SOIC (Package Code SS)
5. PIN CONFIGURATION PDIP 300-MIL
Figure 1c。W25D10, W25D20, W25D40 and W25D80 Pin Assignments, 8-pin PDIP (Package Code DA)
Publication Release Date: July 15, 2006
- 5 - Preliminary - Revision A
5 Page 
W25D10, W25D20, W25D40, W25D80
10. CONTROL AND STATUS REGISTERS
The Read Status Register instruction can be used to provide status on the availability of the Flash
memory array, if the device is write enabled or disabled, and the state of write protection. The Write
Status Register instruction can be used to configure the devices write protection features. See Figure 3.
10.1 STATUS REGISTER
10.1.1 BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing
a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During
this time the device will ignore further instructions except for the Read Status Register instruction (see
tW, tPP, tSE, TBE, and tCE in AC Characteristics). When the program, erase or write status register
instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for
further instructions.
10.1.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing
a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A
write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.
10.1.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, and BP0) are non-volatile read/write bits in the status register (S4,
S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the
Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory
array can be protected from Program and Erase instructions (see Status Register Memory Protection
table). The factory default setting for the Block Protection Bits is 0, none of the array protected. The
Block Protect bits can not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write
Protect (/WP) pin is low.
10.1.4 Top/Bottom Block Protect (TB)
The Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top
(TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.
The TB bit is non-volatile and the factory default setting is TB=0. The TB bit can be set with the Write
Status Register Instruction provided that the Write Enable instruction has been issued. The TB bit can
not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is
low.
10.1.5 Reserved Bits
Status register bit location S6 is reserved for future use. Current devices will read 0 for this bit
location. It is recommended to mask out the reserved bit when testing the Status Register. Doing this
will ensure compatibility with future devices.
- 11 -
Publication Release Date: July 15, 2006
Preliminary - Revision A
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet W25D80.PDF ] | |
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