PDF ICH6 Data sheet ( Hoja de datos )

Número de pieza	ICH6
Descripción	I/O Controller Hub 6
Fabricantes	Intel
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Intel® I/O Controller Hub 6 (ICH6) Family Datasheet For the Intel® 82801FB ICH6, 82801FR ICH6R and 82801FBM ICH6-M I/O Controller Hubs January 2005 Document Number: 301473-002 1 page Contents 5.5.1 LPC Interface ....................................................................................................... 116 5.5.1.1 LPC Cycle Types ................................................................................. 117 5.5.1.2 Start Field Definition............................................................................. 117 5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR) ...........................................118 5.5.1.4 SIZE .....................................................................................................118 5.5.1.5 SYNC ...................................................................................................119 5.5.1.6 SYNC Time-Out ...................................................................................119 5.5.1.7 SYNC Error Indication.......................................................................... 119 5.5.1.8 LFRAME# Usage ................................................................................. 119 5.5.1.9 I/O Cycles ............................................................................................120 5.5.1.10 Bus Master Cycles ............................................................................... 120 5.5.1.11 LPC Power Management ..................................................................... 120 5.5.1.12 Configuration and Intel® ICH6 Implications.......................................... 120 5.6 DMA Operation (D31:F0) .................................................................................................. 121 5.6.1 Channel Priority ................................................................................................... 122 5.6.1.1 Fixed Priority ........................................................................................ 122 5.6.1.2 Rotating Priority ................................................................................... 122 5.6.2 Address Compatibility Mode ................................................................................ 122 5.6.3 Summary of DMA Transfer Sizes ........................................................................ 123 5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words ............................................................................. 123 5.6.4 Autoinitialize.........................................................................................................123 5.6.5 Software Commands ........................................................................................... 124 5.7 LPC DMA .......................................................................................................................... 124 5.7.1 Asserting DMA Requests..................................................................................... 124 5.7.2 Abandoning DMA Requests ................................................................................125 5.7.3 General Flow of DMA Transfers ..........................................................................125 5.7.4 Terminal Count .................................................................................................... 126 5.7.5 Verify Mode..........................................................................................................126 5.7.6 DMA Request De-assertion ................................................................................. 126 5.7.7 SYNC Field / LDRQ# Rules ................................................................................. 127 5.8 8254 Timers (D31:F0)....................................................................................................... 128 5.8.1 Timer Programming ............................................................................................. 128 5.8.2 Reading from the Interval Timer ..........................................................................129 5.8.2.1 Simple Read ........................................................................................ 130 5.8.2.2 Counter Latch Command .....................................................................130 5.8.2.3 Read Back Command .......................................................................... 130 5.9 8259 Interrupt Controllers (PIC) (D31:F0) ........................................................................131 5.9.1 Interrupt Handling ................................................................................................ 132 5.9.1.1 Generating Interrupts ...........................................................................132 5.9.1.2 Acknowledging Interrupts..................................................................... 132 5.9.1.3 Hardware/Software Interrupt Sequence...............................................133 5.9.2 Initialization Command Words (ICWx) ................................................................. 133 5.9.2.1 ICW1 .................................................................................................... 133 5.9.2.2 ICW2 .................................................................................................... 134 5.9.2.3 ICW3 .................................................................................................... 134 5.9.2.4 ICW4 .................................................................................................... 134 5.9.3 Operation Command Words (OCW) ....................................................................134 5.9.4 Modes of Operation ............................................................................................. 134 5.9.4.1 Fully Nested Mode ............................................................................... 134 5.9.4.2 Special Fully-Nested Mode ..................................................................135 5.9.4.3 Automatic Rotation Mode (Equal Priority Devices) ..............................135 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 5 5 Page Contents 7.1.28 7.1.29 7.1.30 7.1.31 7.1.32 7.1.33 7.1.34 7.1.35 7.1.36 7.1.37 7.1.38 7.1.39 7.1.40 7.1.41 7.1.42 7.1.43 7.1.44 7.1.45 7.1.46 7.1.47 7.1.48 7.1.49 7.1.50 7.1.51 7.1.52 7.1.53 7.1.54 7.1.55 7.1.56 7.1.57 7.1.58 7.1.59 7.1.60 7.1.61 CSIR6—Chipset Initialization Register 6 ............................................................. 258 BCR—Backbone Configuration Register .............................................................259 RPC—Root Port Configuration Register..............................................................259 CSIR7—Chipset Initialization Register 7 ............................................................. 260 TRSR—Trap Status Register...............................................................................260 TRCR—Trapped Cycle Register.......................................................................... 260 TWDR—Trapped Write Data Register.................................................................261 IOTRn—I/O Trap Register(0:3)............................................................................261 DMC—DMI Miscellaneous Control Register (Mobile Only) ................................. 262 CSCR1—Chipset Configuration Register 1 .........................................................262 CSCR2—Chipset Configuration Register 2 .........................................................262 PLLMC—PLL Miscellaneous Control Register (Mobile Only)..............................263 TCTL—TCO Configuration Register .................................................................... 263 D31IP—Device 31 Interrupt Pin Register ............................................................ 264 D30IP—Device 30 Interrupt Pin Register ............................................................ 265 D29IP—Device 29 Interrupt Pin Register ............................................................ 266 D28IP—Device 28 Interrupt Pin Register ............................................................ 267 D27IP—Device 27 Interrupt Pin Register ............................................................ 267 D31IR—Device 31 Interrupt Route Register........................................................268 D30IR—Device 30 Interrupt Route Register........................................................269 D29IR—Device 29 Interrupt Route Register........................................................270 D28IR—Device 28 Interrupt Route Register........................................................271 D27IR—Device 27 Interrupt Route Register........................................................272 OIC—Other Interrupt Control Register.................................................................273 RC—RTC Configuration Register ........................................................................273 HPTC—High Precision Timer Configuration Register .........................................274 GCS—General Control and Status Register........................................................274 BUC—Backed Up Control Register ..................................................................... 276 FD—Function Disable Register ...........................................................................277 CG—Clock Gating ............................................................................................... 278 CSIR1—Chipset Initialization Register 1 ............................................................. 279 CSIR2—Chipset Initialization Register 2 ............................................................. 279 CSIR3—Chipset Initialization Register 3 ............................................................. 279 CSIR4—Chipset Initialization Register 4 ............................................................. 279 8 LAN Controller Registers (B1:D8:F0) ..........................................................................281 8.1 PCI Configuration Registers (LAN Controller—B1:D8:F0) ............................................................................................. 281 8.1.1 VID—Vendor Identification Register (LAN Controller—B1:D8:F0) ................................................................................ 282 8.1.2 DID—Device Identification Register (LAN Controller—B1:D8:F0) ................................................................................ 282 8.1.3 PCICMD—PCI Command Register (LAN Controller—B1:D8:F0) ................................................................................ 283 8.1.4 PCISTS—PCI Status Register (LAN Controller—B1:D8:F0) ................................................................................ 284 8.1.5 RID—Revision Identification Register (LAN Controller—B1:D8:F0) ................................................................................ 285 Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 11 11 Page

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