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PDF BD35269HFN Data sheet ( Hoja de datos )
| Número de pieza | BD35269HFN | |
| Descripción | Nch FET Ultra LDO | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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High Performance Regulators for PCs
Nch FET Ultra LDO
for Desktop PCs
BD35269HFN
No.11030ECT12
●Description
The BD35269HFN ultra low-dropout linear chipset regulator operates from a very low input supply, and offers ideal
performance in low input voltage to low output voltage applications. It incorporates a built-in N-MOSFET power transistor to
minimize the input-to-output voltage differential to the ON resistance (RON MAX=400mΩ) level. By lowering the dropout
voltage in this way, the regulator realizes high current output (Iomax=1.0A) with reduced conversion loss, and thereby
obviates the switching regulator and its power transistor, choke coil, and rectifier diode. Thus, the 35269HFN designed to
enable significant package profile downsizing and cost reduction. In BD35269HFN, The NRCS (soft start) function enables a
controlled output voltage ramp-up, which can be programmed to whatever power supply sequence is required.
●Features
1) Internal high-precision reference voltage circuit (0.65V±1%)
2) Internal high-precision output voltage circuit
3) Built-in VCC undervoltage lockout circuit (VCC=3.80V)
4) NRCS (soft start) function reduces the magnitude of in-rush current
5) Internal Nch MOSFET driver offers low ON resistance (250mΩ typ)
6) Built-in short circuit protection (SCP)
7) Built-in current limit circuit (1.0A min)
8) Built-in thermal shutdown (TSD) circuit
9) Small package HSON8 : 2.9mm×3.0mm×0.6mm
10) Tracking function
●Applications
Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances
●Absolute maximum ratings (Ta=25℃)
Parameter
Symbol
Ratings
Unit
Input Voltage 1
Input Voltage 2
Maximum Output Current
VCC
VIN
IO
+6.0 *1
+6.0 *1
1*1
V
V
A
Enable Input Voltage
Power Dissipation 1
VEN -0.3～+6.0 V
Pd1 0.63 *2 W
Power Dissipation 2
Pd2 1.35 *3 W
Power Dissipation 3
Pd3 1.75*4 W
Operating Temperature Range
Topr
-10～+100
℃
Storage Temperature Range
Tstg
-55～+125
℃
Maximum Junction Temperature Tjmax
+150
℃
*1 Should not exceed Pd.
*2 Reduced by 5.04mW/℃ for each increase in Ta≧25℃
(when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer, copper foil area : less than 0.2%)
*3 Reduced by 10.8mW/℃ for each increase in Ta≧25℃
(when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer,copper foil area : less than 7.0%)
*4 Reduced by 14.0mW/℃ for each increase in Ta≧25℃
(when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 1-layer,copper foil area : less than 65.0%)
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
1/15
2011.01 - Rev.C
1 page  
BD35269HFN
Technical Note
●Block Diagram
VCC
VCC
1
C1
EN
2
Reference
Block
VREF1
NRCS0.3.
VREF1×0.4
FB
TSD
UVLO2
VIN
UVLOLATCH
VCC
EN
UVLO1
UVLO1
CL
VCC
VREF2
Current
Limit
VCC
NRCS
SCP/TSD LATCH
LATCH
EN
UVLO1
CL
UVLO1
UVLO2
TSD
SCP
EN
NRCS
3
CNRCS
EN/UVLO
NRCS
R2
R1
VIN
4
VIN
C2
VO
5
6
VOS
R2
7
FB
R1
VO
CFB C3
8
GND
●Pin Layout
VCC 1
EN 2
NRCS 3
VIN 4
6
FIN
●Pin Function Table
PIN No. PIN name
PIN Function
8 GND
7 FB
6 VOS
1 VCC Power Supply Pin
2 EN Enable Input Pin
3
NRCS
In-rush Current Protection (NRCS)
Capacitor Connection Pin
4 VIN Input Voltage Pin
5 VO Output Voltage Pin
5 VO
6 VOS Output Voltage Control Pin
7 FB Reference Voltage Feedback Pin
8 GND Ground Pin
- FIN Connected to heatsink and GND
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
5/15
2011.01 - Rev.C
5 Page 
BD35269HFN
Technical Note
●Heat Loss
Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed
temperature limits, and thermal design should allow sufficient margin from the limits.
1. Ambient temperature Ta can be no higher than 100℃.
2. Chip junction temperature (Tj) can be no higher than 150℃.
Chip junction temperature can be determined as follows:
①Calculation based on ambient temperature (Ta)
Tj=Ta+θj-a×W
＜Reference values＞
θj-a:HSON8 198.4℃/W
92.4℃/W
71.4℃/W
1-layer substrate (copper foil area : below 0.2%)
1-layer substrate (copper foil area : 7%)
2-layer substrate (copper foil area : 65%)
Substrate size: 70×70×1.6mm3 (substrate with thermal via)
It is recommended to layout the VIA for heat radiation in the GND pattern of reverse (of IC) when there is the GND pattern in
the inner layer (in using multiplayer substrate). This package is so small (size: 2.9mm×3.0mm) that it is not available to
layout the VIA in the bottom of IC. Spreading the pattern and being increased the number of VIA like the figure below enable
to get the superior heat radiation characteristic. (This figure is the image. It is recommended that the VIA size and the
number is designed suitable for the actual situation.).
Most of the heat loss that occurs in the BD35269HFN is generated from the output Nch FET. Power loss is determined by the
total VIN-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current
conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in mind that heat
dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the
BD3523XHFN) make certain to factor conditions such as substrate size into the thermal design.
Power consumption (W) = Input voltage (VIN) - Output voltage (VO) Io(Ave)
Example)
Where VIN=1.7V, Vo=1.2V, Io(Ave) = 1A,
Power consumption (W) = 1.7 (V) - 1.2 (V) 1.0(A)
= 0.5(W)
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
11/15
2011.01 - Rev.C
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet BD35269HFN.PDF ] | |
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