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PDF LC877364A Data sheet ( Hoja de datos )
| Número de pieza | LC877364A | |
| Descripción | 8-Bit Single Chip Microcontroller | |
| Fabricantes | Sanyo | |
| Logotipo |  |
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CMOS IC
LC877372A/64A/56A/48A
8-Bit Single Chip Microcontroller
Under Development
LC877372A
8 bit Single Chip Microcontroller incorporating 72KB ROM and 2048 byte RAM on chip
LC877364A
8 bit Single Chip Microcontroller incorporating 64KB ROM and 2048 byte RAM on chip
LC877356A
8 bit Single Chip Microcontroller incorporating 56KB ROM and 2048 byte RAM on chip
LC877348A
8 bit Single Chip Microcontroller incorporating 48KB ROM and 2048 byte RAM on chip
Overview
The LC877372A, LC877364A LC877356A and LC877348A are 8-bit single chip microcontrollers with the
following on-chip functional blocks :
- CPU: operable at a minimum bus cycle time of 100 ns
- On-chip ROM Maximum Capacity : LC877372A 72K bytes
LC877364A 64K bytes
LC877356A 56K bytes
LC877348A 48K bytes
- On-chip RAM capacity: 2048 bytes
- LCD controller / driver
- 16 bit timer / counter (can be divided into two 8 bit timers)
- 16 bit timer / PWM (can be divided into two 8 bit timers)
- Four 8-bit timer with prescalers
- Timer for use as date / time clock
- Synchronous serial I/O port (with automatic block transmit / receive function)
- Asynchronous / synchronous serial I/O port
- 15-channel × 8-bit AD converter
- Small signal detector
Ver:1.01
83101
SYSTEM-BIZ S. Kubota 1/26
1 page  
LC877372A/64A/56A/48A
-HOLD mode
HOLD mode is used to reduce power consumption. Program execution and peripheral circuits
are stopped.
1) CF, RC and crystal oscillation circuits stop automatically.
2) Released by any of the following conditions.
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, INT2
(3) Port 0 interrupt
-X’tal HOLD made
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base timer are stopped.
1) CF and RC oscillation circuits stop automatically.
2) Crystal oscillator operation is kept in its state at HOLD mode inception.
3) Released by any of the following conditions
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, INT2
(3) Port 0 interrupt
(4) Base-timer interrupt
(20) Package
- QIP100E
- TQFP100
(21) Development tools
- Evaluation chip : LC876093
- Emulator: EVA62S + ECB876600 (Evaluation chip board) + SUB877300 + POD100QFP or
POD100SQFP (Type B):
: ICE-B877300 + SUB877300 + POD100QFPor POD100SQFP (Type B)
- Flash ROM version: LC87F73C8A
5/26
5 Page 
LC877372A/64A/56A/48A
Port Configuration
Port form and pull-up resistor options are shown in the following table.
Port status can be read even when port is set to output mode.
Terminal
P00 to P07
Option applies
to:
each bit
Options
1
CMOS
Output Form
P10 to P17
P30 to P35
P70
P71 to P73
P80 to P87
S0/PA0 to
S47/PF7
each bit
each bit
–
–
–
–
2
1
2
1
2
None
None
None
None
Nch-open drain
CMOS
Nch-open drain
CMOS
Nch-open drain
Nch-open drain
CMOS
Nch-open drain
CMOS
Pull-up resistor
Programmable
(Note 1)
None
Programmable
Programmable
Programmable
None
Programmable
Programmable
None
Programmable
COM0/PL0 to
COM3/PL3
V1/PL4 to
V3/PL6
XT1
–
–
–
None Input only
None Input only
None Input only
None
None
None
XT2
– None Output for 32.768kHz crystal
None
oscillation
Note 1 Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00-03, P04-07).
* Note 1: Connect as follows to reduce noise on VDD.
VSS1, VSS2 and VSS3 must be connected together and grounded.
*Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD3 as the power supply for
ports. When the VDD3 is not backed up, the port level does not become “H” even if the port latch is
in the “H” level. Therefore, when the VDD3 is not backed up and the port latch is “H” level, the port
level is unstable in the HOLD mode, and the back up time becomes shorter because the through
current runs from VDD to GND in the input buffer.
If VDD3 is not backed up, output “L” by the program or pull the port to “L” by the external circuit
in the HOLD mode so that the port level becomes “L” level and unnecessary current consumption is
prevented.
Power
supply
LSI
VDD1
Back-up capacitors *2 VDD2
VDD3
VSS1 VSS2VSS3
11/26
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet LC877364A.PDF ] | |
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