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PDF NCP3170ADR2G Data sheet ( Hoja de datos )

Número de pieza NCP3170ADR2G
Descripción Synchronous PWM Switching Converter
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No Preview Available ! NCP3170ADR2G Hoja de datos, Descripción, Manual

NCP3170
Synchronous PWM
Switching Converter
The NCP3170 is a flexible synchronous PWM Switching Buck
Regulator. The NCP3170 operates from 4.5 V to 18 V, sourcing up to
3 A and is capable of producing output voltages as low as 0.8 V.
The NCP3170 also incorporates current mode control. To reduce the
number of external components, a number of features are internally set
including soft start, power good detection, and switching frequency.
The NCP3170 is currently available in an SOIC8 package.
Features
4.5 V to 18 V Operating Input Voltage Range
90 mW High-Side, 25 mW Low-Side Switch
FMEA Fault Tolerant During Pin Short Test
3 A Continuous Output Current
Fixed 500 kHz and 1 MHz PWM Operation
Cycle-by-Cycle Current Monitoring
1.5% Initial Output Accuracy
Internal 4.6 ms Soft-Start
Short-Circuit Protection
Turn on Into Pre-bias
Power Good Indication
Light Load Efficiency
Thermal Shutdown
These are Pb-Free Devices
Typical Applications
Set Top Boxes
DVD/Blurayt Drives and HDD
LCD Monitors and TVs
Cable Modems
PCIe Graphics Cards
Telecom/Networking/Datacom Equipment
Point of Load DC/DC Converters
VIN
C1
22 mF
VIN L1 4.7 mH
VSW
EN
NCP3170
PG
3.3 V
R1
COMP
CC
AGND
FB1
PGND
C2, C3
22 mF
R2
RC
http://onsemi.com
SOIC8 NB
CASE 751
MARKING DIAGRAM
8
3170x
ALYW
G
1
3170x
x
A
L
Y
W
G
= Specific Device Code
= A or B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
PIN CONNECTIONS
PGND
VIN
AGND
FB
(Top View)
VSW
PG
EN
COMP
ORDERING INFORMATION
Device
Package
Shipping
NCP3170ADR2G SOIC8 2,500/Tape & Reel
(PbFree)
NCP3170BDR2G SOIC8 2,500/Tape & Reel
(PbFree)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2014
September, 2014 Rev. 5
1
Publication Order Number:
NCP3170/D

1 page




NCP3170ADR2G pdf
NCP3170
TYPICAL PERFORMANCE CHARACTERISTICS
(Circuit from Figure 1, TA = 25°C, VIN = VEN = 12 V, VOUT = 3.3 V unless otherwise specified)
Figure 3. Light Load (DCM) Operation 1 ms/DIV
Figure 4. Full Load (CCM) Operation 1 ms/DIV
Figure 5. StartUp into Full Load 1 ms/DIV
Figure 6. ShortCircuit Protection 200 ms /DIV
Figure 7. 50% to 100% Load Transient 100 ms/DIV
Figure 8. 3.3 V Turn on into 1 V PreBias 1 ms /DIV
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NCP3170ADR2G arduino
NCP3170
The part can be enabled with standard TTL or high voltage
logic by using the configuration below.
4.5 V18 V
VIN
C1IN
R1LOG
R2LOG
C1LOG
EN
NCP3170
AGND
Figure 32. Logic Turn-on
The enable can also be used for power sequencing in
conjunction with the Power Good (PG) pin as shown in
Figure 33. The enable pin can either be tied to the output
voltage of the master voltage or tied to the input voltage with
a resistor to the PG pin of the master regulator.
4.5 V18 V
VIN
EN
PG
AGND
VSW
FB
NCP3170
4.5 V18 V
VIN
EN
VSW
Vo1
Vo1
Vo2
Vo2
AGND
FB
NCP3170
Figure 33. Enable Two Converter Power Sequencing
Once the part is enabled, the internal reference voltage is
slewed from ground to the set point of 800 mV. The slewing
process occurs over a 4.5 ms period, reducing the current
draw from the upstream power source, reducing stress on
internal MOSFETS, and ensuring the output inductor does
not saturate during start-up.
Pre-Bias Start-up
When starting into a pre-bias load, the NCP3170 will not
discharge the output capacitors. The soft start begins with
the internal reference at ground. Both the high side switch
and low side switches are turned off. The internal reference
slowly raises and the OTA regulates the output voltage to the
divided reference voltage. In a pre-biased condition, the
voltage at the FB pin is higher than the internal reference
voltage, so the OTA will keep the COMP voltage at ground
potential. As the internal reference is slewed up, the COMP
pin is held low until the FB pin voltage surpasses the internal
reference voltage, at which time the COMP pin is allowed
to respond to the OTA error signal. Since the bottom of the
PWM ramp is at 0.6 V there will be a slight delay between
the time the internal reference voltage passes the FB voltage
and when the part starts to switch. Once the COMP error
signal intersects with the bottom of the ramp, the high side
switch is turned on followed by the low side switch. After the
internal reference voltage has surpassed the FB voltage, soft
start proceeds normally without output voltage discharge.
Power Good
The output voltage of the buck converter is monitored at
the feedback pin of the output power stage. Two
comparators are placed on the feedback node of the OTA to
monitor the operating window of the feedback voltage as
shown in Figure 34. All comparator outputs are ignored
during the soft start sequence as soft start is regulated by the
OTA since false trips would be generated. Further, the PG
pin is held low until the comparators are evaluated. PG state
does not affect the switching of the converter. After the soft
start period has ended, if the feedback is below the reference
voltage of comparator 1 (VFB < 0.726), the output is
considered operational undervoltage (OUV). The device
will indicate the under voltage situation by the PG pin
remaining low with a 100 kW pull-up resistance. When the
feedback pin voltage rises between the reference voltages of
comparator 1 and comparator 2 (0.726 < VFB < 0.862),
then the output voltage is considered power good and the PG
pin is released. Finally, if the feedback voltage is greater than
comparator 2 (VFB > 0.862), the output voltage is
considered operational overvoltage (OOV). The OOV will
be indicated by the PG pin remaining low. A block diagram
of the OOV and OUV functionality as well as a graphical
representation of the PG pin functionality is shown in
Figures 34 through 36.
FB 800 mV
+
SOFT
Comp 2 Start
+ Complete
862 mV
12 V
100 kW
PG
726 mV +
Comp 1
Figure 34. OOV and OUV System
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