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Número de pieza | FTT1010-M | |
Descripción | Frame Transfer CCD Image Sensor | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
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No Preview Available ! IMAGE SENSORS
FTT1010-M
Frame Transfer CCD Image Sensor
Product specification
File under Image Sensors
1999 September 21
Philips
Semiconductors
TRAD
1 page Philips Semiconductors
Frame Transfer CCD Image Sensor
Product specification
FTT1010-M
Specifications
ABSOLUTE MAXIMUM RATINGS1
GENERAL:
storage temperature
ambient temperature during operation
voltage between any two gates
DC current through any clock phase (absolute value)
OUT current (no short circuit protection)
VOLTAGES IN RELATION TO VPS:
VNS, SFD, RD
VCS, SFS
all other pins
VOLTAGES IN RELATION TO VNS:
SFD, RD
VCS, SFS, VPS
all other pins
VNS3
VPS
SFD
SFS
VCS
OG
RD
DC CONDITIONS2
N substrate
P substrate
Source Follower Drain
Source Follower Source
Current Source
Output Gate
Reset Drain
MIN.
-55
-40
-20
-0.2
0
-0.5
-8
-5
-15
-30
-30
MAX.
+80
+60
+20
+2.0
10
+30
+5
+25
+0.5
+0.5
+0.5
UNIT
°C
°C
V
µA
mA
V
V
V
V
V
V
MIN. [V]
18
1
16
-
-5
4
13
TYPICAL [V]
24
3
20
0
0
6
15.5
MAX. [V]
28
7
24
-
3
8
18
MAX. [mA]
15
15
4.5
1
-
-
-
AC CLOCK LEVEL CONDITIONS2
IMAGE CLOCKS:
A-clock amplitude during integration and hold
A-clock amplitude during vertical transport (duty cycle=5/8)4
A-clock low level
Charge Reset (CR) level on A-clock 5
STORAGE CLOCKS:
B-clock amplitude during hold
B-clock amplitude during vertical transport (duty cycle=5/8)
OUTPUT REGISTER CLOCKS:
C-clock amplitude (duty cycle during hor. transport = 3/6)
C-clock low level
Summing Gate (SG) amplitude
Summing Gate (SG) low level
OTHER CLOCKS:
Reset Gate (RG) amplitude
Reset Gate (RG) low level
Charge Reset (CR) pulse on Nsub 5
MIN.
8
10
-5
8
10
4.75
2
5
0
TYPICAL
MAX.
UNIT
10 V
14 V
0V
-5 V
10 V
14 V
5 5.25 V
3.5 V
10 10 V
3.5 V
10 10 V
3V
10 10 V
1 During Charge Reset it is allowed to exceed maximum rating levels (see note5).
2 All voltages in relation to SFS.
3 To set the VNS voltage for optimal Vertical Anti-Blooming (VAB), it should be adjustable between minimum and maximum values.
4 Three-level clock is preferred for maximum charge; the swing during vertical transport should be 4V higher than the voltage during integration.
A two level clock (typically 10V) can be used if a lower maximum charge handling capacity is allowed.
5 Charge Reset can be achieved in two ways:
• The typical CR level is applied to all image clocks simultaneously (preferred).
• The typical A-clock low level is applied to all image clocks; for proper CR, an additional Charge Reset pulse on VNS is required.This will also affect
the charge handling capacity in the storage areas.
1999 September
5
5 Page Philips Semiconductors
Frame Transfer CCD Image Sensor
Product specification
FTT1010-M
LINEAR/SATURATION
Full-well capacity saturation level (Qmax) 1
Full-well capacity shading (Qmax, shading) 2
Full-well capacity linear operation (Qlin) 3
Charge handling capacity 4
Overexposure 5 handling
MIN.
250
200
100
TYPICAL
MAX.
500 600
10 50
350
600
200
UNIT
kel.
%
kel.
kel.
x Qmax level
1 Qmax is determined from the lowpass filtered image.
2 Qmax, shading is the maximum difference of the full-well charges of all pixels, relative to Qmax.
3 The linear full-well capacity Qlin is calculated from linearity test (see dynamic range). The evaluation test guarantees 97% linearity.
4 Charge handling capacity is the largest charge packet that can be transported through the register and read-out through the output buffer.
5 Overexposure over entire area while maintaining good Vertical Anti-Blooming (VAB). It is tested by measuring the dark line.
Charge Handling vs. Integration/Transport Voltage
600
10V/14V
500
9V/13V
400
300 8V/12V
200
100
0
1 2 3 4 56
Exposure (arbitrary units)
Figure 10 - Charge handling versus integration/transport voltage
1999 September
11
11 Page |
Páginas | Total 17 Páginas | |
PDF Descargar | [ Datasheet FTT1010-M.PDF ] |
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