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PDF SP5610 Data sheet ( Hoja de datos )

Número de pieza SP5610
Descripción 1.3GHz BI-DIRECTIONAL I2C BUS CONTROLLED SYNTHESISER
Fabricantes Zarlink Semiconductor 
Logotipo Zarlink Semiconductor Logotipo



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No Preview Available ! SP5610 Hoja de datos, Descripción, Manual

FEBRUARY 1997
ADVANCE INFORMATION
D.S. 3920 3.3
SP5610
1.3GHz BI–DIRECTIONAL I2C BUS CONTROLLED SYNTHESISER
(Supersedes edition in 1996 Media IC Handbook, HB4599–1.0)
The SP5610 is a single chip frequency synthesiser
designed for TV tuning systems. Control data is entered in the
standard I2C BUS format. The device contains 1 addressable
current limited output and 4 addressable bi–directional open
collector ports one of which is a 3 bit ADC. The information on
these ports can be read via the I2C BUS. The device has one
fixed I2C BUS address and 3 programmable addresses,
programmed by applying a specific input voltage to the P3
current limited output. This enables 2 or more synthesisers to
be used in a system.
FEATURES
J Complete 1.3GHz Single chip System
J High Sensitivity RF Inputs
J Programmable via I2C Bus
J On Chip oscillator with 1kW negative resistance
J Low power consumption (5V, 20mA)
J Low Radiation
J Phase Lock Detector
J Varactor Drive Amp Disable
J 5 Controllable Outputs
J 5 Level ADC
J Variable I2C BUS Address For Multi Tuner
Applications
J ESD Protection *
J Switchable 512/1024 Reference Divider
J Pin and Function Compatible with SP5510S [
* Normal ESD handling procedures should be observed.
[ The SP5510S does not have a switchable
reference division ratio.
APPLICATIONS
J Satellite TV when combined with SP4902 2.5GHz
prescaler
J Cable Tuning Systems
J VCR’s
CHARGE PUMP
CRYSTAL Q1
CRYSTAL Q2
SDA
SCL
[ I/O PORT P7
* I/O PORT P6
[ I/O PORT P5
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
DRIVE OUTPUT
V EE
RF INPUT
RF INPUT
V CC
NC
P3 OUTPUT PORT/
ADD SELECT
I/O PORT P4 [
MP16
[ = Logic level I/O
* = 3–bit ADC input
Fig. 1 Pin connections – top view
ORDERING INFORMATION
SP5610S/KG/MPAS (Tubes)
SP5610S/KG/MPAD (Tape and Reel)

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SP5610 pdf
SP5610
ADDRESS
PROGRAMMABLE
DIVIDER
PROGRAMMABLE
DIVIDER
CONTROL DATA
IO PORT CONTROL
DATA
ADDRESS
STATUS BYTE
MSB
1
1
0
0
0
MA1
MA0
0 214 213 212 211 210 29
27 26 25 24 23 22 21
1 CP T1 T0 TS2 TS1 TS0
P7 P6 P5 P4 P3
X
X
Table 1 Write data format (MSB is transmitted first)
1
POR
1
0
0
0
MA1
MA0
FL I2 I1 I0 A2 A1
Table 2 Read data format (MSB is transmitted first)
LSB
0
28
20
OS
X
1
A0
A:
MA1, MA0:
CP:
T1:
T0:
TS2, TS1, TS0:
OS:
P7,P6,P5,P4,P3:
POR:
FL:
I2, I1, I0:
A2, A1, A0:
X:
Acknowledge bit
Variable address bits (see Table 4)
Charge pump current select
Test mode enable
Charge pump disable
Operation mode control bits (see Table 5)
Varactor drive Output disable Switch
Control output states
Power On Reset indicator
Phase Lock detect Flag
Digital information from Ports P7, P5 and P4, respectively
5 Level ADC data from P6 (see Table 3)
Don’t care
A Byte 1
A Byte 2
A Byte 3
A Byte 4
A Byte 5
A Byte 1
A Byte 2
A2 A1 A0
Voltage input to P6
100
0.6VCC to 13.2V
011
0.45VCC to 0.6VCC
010
0.3VCC to 0.45VCC
001
0.15VCC to 0.3VCC
000
0 to 0.15VCC
Table 3 ADC levels
MA1
0
0
1
1
MA0
Voltage input to P3
0 0 – 0.2VCC
1 ALWAYS VALID
0 0.3VCC – 0.7VCC
1 0.8VCC – 13.2V
Table 4 Address selection
T1 TS2 TS1
0XX
0XX
100
101
110
110
111
X=don’t care
For further details of test modes see Table 6.
TS0 OPERATION MODE DESCRIPTION
0 Normal operation, test modes disabled, reference divider ratio=1024
1 Normal operation, test modes disabled, reference divider ratio=512
X Charge pump source (down). Status byte bit FL set to 0
X Charge pump sink (up). Status byte bit FL set to 1
0 Ports P4,P5,P6,P7 set to state X
1 Port P7=FPD/2; P4,P5,P6 set to state X
X Port P7=FPD; P6=FCOMP; P4, P5 set to state X
Table 5 Operation modes
Fig. 3 Data formats
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SP5610 arduino
SP5610
TEST MODES
As explained earlier in the data sheet, the device can be programmed into a number of test modes. These are invoked by
programming the following HEX codes into Byte 4. The most commonly used codes are shown in Table 6
DESCRIPTION
Normal operation, REF DIV =1024
Normal operation, REF DIV = 512
Charge Pump Source (Down), FL SET to 0
Charge Pump Sink (up), FL SET to 1
Port P7 = FPD/2
Port P7 = FPD; P6 = FCOMP
Charge Pump Disable, REF DIV 512
Varactor Line Disable, REF DIV 512
Charge Pump and Varactor Line Disable, REF DIV 512
Table 6 Useful test modes.
HEX CODE (BYTE 4)
CP HI MODE
CC
CE
E2
E6
EA
EE
DE
CF
DF
CP LO MODE
8C
8E
A2
A6
AA
AE
9E
8F
9F
Other codes will also apply due to ‘Don’t Care’ conditions,
which are assumed to be 1 in the above Table.
NOTE:
When looking at FPD or FCOMP signals from Ports P7 and
P6, Byte 4 should be sent twice, firstly to set the desired
reference divider ratio, (see Table 6) then secondly to switch
on the chosen test mode.
The pulses can then be measured by simply connecting an
oscilloscope or counter to the relevant output pin on the test
board.
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