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PDF ICS9UMS9610 Data sheet ( Hoja de datos )

Número de pieza ICS9UMS9610
Descripción PC MAIN CLOCK
Fabricantes IDT 
Logotipo IDT Logotipo



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No Preview Available ! ICS9UMS9610 Hoja de datos, Descripción, Manual

PC MAIN CLOCK
Recommended Application:
Poulsbo Based Ultra-Mobile PC (UMPC) - CK610
Output Features:
• 3 - CPU low power differential push-pull pairss
• 3 - SRC low power differential push-pull pairs
• 1 - LCD100 SSCD low power differential
push-pull pair
• 1 - DOT96 low power differential push-pull
pair
• 1 - REF, 14.31818MHz, 3.3V SE output
Pin Configuration
Advance Information
ICS9UMS9610
Features/Benefits:
• Supports Dothan ULV CPUs with 100 to
200 MHz CPU outputs
• Dedicated TEST/SEL and TEST/MODE pins
saves isolation resistors on pins
• CPU STOP# input for power manangment
• Fully integrated Vreg
• Integrated series resistors on differential
outputs
• 1.5V VDD IO, 1.5V VDD core, 3.3V VDD
supply pin for REF
48 47 46 45 44 43 42 41 40 39 38 37
CPU_STOP#_3.3 1
36 *CR#2_1.5
CLKPWRGD#/PD_3.3 2
35 SRCT2_LPR
X2 3
34 SRCC2_LPR
X1 4
33 GNDSRC
VDDREF_3.3 5
32 SRCT1_LPR
REF_3.3_2x 6
GNDREF 7
9UMS9610
31 SRCC1_LPR
30 VDDIO_1.5
VDDCORE_1.5 8
29 VDDCORE_1.5
FSC_L_1.5 9
28 *CR#1_1.5
TEST_MODE_1.5 10
27 SRCT0_LPR
TEST_SEL_1.5 11
26 SRCC0_LPR
SCLK_3.3 12
25 GNDSRC
13 14 15 16 17 18 19 20 21 22 23 24
IDTTM/ICSTM PC MAIN CLOCK
48-pin MLF, 6x6 mm, 0.4mm pitch
* indicates inputs with internal pull up of ~10Kohm to 1.5V
1
1336—07/21/08

1 page




ICS9UMS9610 pdf
ICS9UMS9610
PC MAIN CLOCK
Advance Information
Absolute Maximum Ratings
PARAMETER
SYMBOL
3.3V Supply Voltage
VDDxxx_3.3
1.5V Supply Voltage
VDDxxx_1.5
3.3_Input High Voltage
VIH3.3
CONDITIONS
Supply Voltage
Supply Voltage
3.3V Inputs
1.5_Input High Voltage
VIH1.5
1.5V Inputs
Minimum Input Voltage
Storage Temperature
VIL
Ts
Any Input
-
Input ESD protection
ESD prot
Human Body Model
Notes:
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied, nor guaranteed.
3 Maximum input voltage is not to exceed maximum VDD
MIN
GND - 0.5
-65
2000
MAX UNITS
3.9 V
2.1 V
VDD_3.3+
0.3V
V
VDD_1.5+
0.3V
V
V
150 °C
V
Notes
1,2
1,2
1,2,3
1,2,3
1
1,2
1,2
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
Ambient Operating Temp
3.3V Supply Voltage
1.5V Supply Voltage
3.3V Input High Voltage
3.3V Input Low Voltage
1.5V Input High Voltage
1.5V Input Low Voltage
Input Leakage Current
Input Leakage Current
Output High Voltage
Output Low Voltage
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
Operating Supply Current
Power Down Current
SYMBOL
Tambient
VDDxxx_3.3
VDDxxx_1.5
VIHSE3.3
VILSE3.3
VIHSE1.5
VILSE1.5
IIN
IINRES
VOHSE
VOLSE
VIH_FS
CONDITIONS
No Airflow
3.3V +/- 5%
1.5V +/- 5%
Single-ended inputs
Single-ended inputs
Single-ended inputs
Single-ended inputs
VIN = VDD , VIN = GND
Inputs with pull or pull down
resistors
VIN = VDD , VIN = GND
Single-ended output, IOH = -1mA
Single-ended output, IOL = 1 mA
1.5 V +/-5%
MIN
0
3.135
1.425
2
VSS - 0.3
1.2
VSS - 0.3
-5
MAX UNITS Notes
70 °C 1
3.465
V
1
1.575
V
1
VDDxx_3.3 +
0.3
V
1
0.8 V 1
VDDxxx_1.5 +
0.3
V
1
0.3 V 1
5 uA 1
-200
200 uA 1
2.4 V 1
0.4 V 1
0.7 1.5 V 1
VIL_FS
IDD_3.3
IDD_DEFAULT1.5
IDD_LCDEN1.5
IDD_IO1.5
IDD_PD3.3
IDD_PD1.5CORE
1.5 V +/-5%
3.3V supply
1.5V core supply, LCDPLL off
1.5V core supply, LCDPLL enabled
1.5V supply, Differential IO current,
all outputs enabled
3.3V supply, Power Down Mode
1.5V CORE supply, Power Down
Mode
VSS - 0.3
0.35
10
45
55
15
0.5
0.5
V
mA
mA
mA
mA
mA
mA
1
1
1
1
1
1
1
IDD_PD1.5IO 1.5V IO supply, Power Down Mode
0.1 mA 1
Input Frequency
Pin Inductance
Input Capacitance
Spread Spectrum Modulation
Frequency
Fi
Lpin
CIN
COUT
CINX
fSSMOD
VDD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
Triangular Modulation
15
MHz
2
7 nH 1
1.5 5 pF 1
6 pF 1
3 5 pF 1
30 33 kHz 1
IDTTM/ICSTM PC MAIN CLOCK
5
1336—07/21/08

5 Page





ICS9UMS9610 arduino
ICS9UMS9610
PC MAIN CLOCK
Advance Information
Byte
Bit(s)
7
6
5
4
3
2
1
0
2 Output Enable Register
Pin #
Name
Description
Type
CPU0 Enable
This bit controls whether the CPU[0] output RW
buffer is enabled or not.
CPU1 Enable
This bit controls whether the CPU[1] output RW
buffer is enabled or not.
CPU2 Enable
This bit controls whether the CPU[2] output
buffer is enabled or not.
RW
SRC0 Enable
This bit controls whether the SRC[0] output RW
buffer is enabled or not.
SRC1 Enable
This bit controls whether the SRC[1] output RW
buffer is enabled or not.
SRC2 Enable
This bit controls whether the SRC[2] output RW
buffer is enabled or not.
DOT Enable
This bit controls whether the DOT output
buffer is enabled or not.
RW
LCD100 Enable This bit controls whether the LCD output buffer RW
is enabled or not.
0
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
1
1 = Enabled
Default
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
Byte
Bit(s)
7
6
5
4
3
2
1
0
3 Output Control Register
Pin #
Name
Description
Reserved
Reserved
REF Enable
This bit controls whether the REF output
buffer is enabled or not.
REF Slew
These bits control the edge rate of the REF
clock.
CPU0 Stop
Enable
CPU1 Stop
Enable
This bit controls whether the CPU[0] output
buffer is free-running or stoppable. If it is set
to stoppable the CPU[0] output buffer will be
disabled with the assertion of CPU_STP#.
This bit controls whether the CPU[1] output
buffer is free-running or stoppable. If it is set
to stoppable the CPU[1] output buffer will be
disabled with the assertion of CPU_STP#.
Type
RW
RW
RW
RW
01
0 = Disabled 1 = Enabled
00 = Slow Edge Rate
01 = Medium Edge Rate
10 = Fast Edge Rate
11 = Reserved
Free Running Stoppable
Free Running Stoppable
CPU2 Stop
Enable
This bit controls whether the CPU[2] output
buffer is free-running or stoppable. If it is set
to stoppable the CPU[2] output buffer will be RW Free Running
disabled with the assertion of CPU_STP#.
Stoppable
Default
0
0
1
10
0
0
0
IDTTM/ICSTM PC MAIN CLOCK
11
1336—07/21/08

11 Page







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