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PDF 3400 Data sheet ( Hoja de datos )

Número de pieza 3400
Descripción 5 Series Chipset
Fabricantes Intel 
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Intel® 5 Series Chipset and
Intel® 3400 Series Chipset
Datasheet
January 2012
Document Number: 322169-004

1 page




3400 pdf
5.8
5.9
5.10
5.11
5.12
5.13
5.7.2.3
Read Back Command........................................................... 152
8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 153
5.8.1 Interrupt Handling............................................................................. 154
5.8.1.1
Generating Interrupts .......................................................... 154
5.8.1.2
Acknowledging Interrupts..................................................... 154
5.8.1.3
Hardware/Software Interrupt Sequence ................................. 155
5.8.2 Initialization Command Words (ICWx).................................................. 155
5.8.2.1
ICW1................................................................................. 155
5.8.2.2
ICW2................................................................................. 156
5.8.2.3
ICW3................................................................................. 156
5.8.2.4
ICW4................................................................................. 156
5.8.3 Operation Command Words (OCW)...................................................... 156
5.8.4 Modes of Operation ........................................................................... 156
5.8.4.1
Fully Nested Mode ............................................................... 156
5.8.4.2
Special Fully-Nested Mode .................................................... 157
5.8.4.3
Automatic Rotation Mode (Equal Priority Devices) .................... 157
5.8.4.4
Specific Rotation Mode (Specific Priority) ................................ 157
5.8.4.5
Poll Mode ........................................................................... 157
5.8.4.6
Edge and Level Triggered Mode............................................. 158
5.8.4.7
End of Interrupt (EOI) Operations ......................................... 158
5.8.4.8
Normal End of Interrupt ....................................................... 158
5.8.4.9
Automatic End of Interrupt Mode........................................... 158
5.8.5 Masking Interrupts ............................................................................ 159
5.8.5.1
Masking on an Individual Interrupt Request ............................ 159
5.8.5.2
Special Mask Mode .............................................................. 159
5.8.6 Steering PCI Interrupts ...................................................................... 159
Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 160
5.9.1 Interrupt Handling............................................................................. 160
5.9.2 Interrupt Mapping ............................................................................. 160
5.9.3 PCI / PCI Express* Message-Based Interrupts ....................................... 161
5.9.4 IOxAPIC Address Remapping .............................................................. 161
5.9.5 External Interrupt Controller Support ................................................... 161
Serial Interrupt (D31:F0) ................................................................................. 162
5.10.1 Start Frame...................................................................................... 162
5.10.2 Data Frames..................................................................................... 163
5.10.3 Stop Frame ...................................................................................... 163
5.10.4 Specific Interrupts Not Supported Using SERIRQ ................................... 163
5.10.5 Data Frame Format ........................................................................... 164
Real Time Clock (D31:F0)................................................................................. 165
5.11.1 Update Cycles................................................................................... 165
5.11.2 Interrupts ........................................................................................ 166
5.11.3 Lockable RAM Ranges ........................................................................ 166
5.11.4 Century Rollover ............................................................................... 166
5.11.5 Clearing Battery-Backed RTC RAM ....................................................... 166
Processor Interface (D31:F0) ............................................................................ 168
5.12.1 Processor Interface Signals and VLW Messages ..................................... 168
5.12.1.1 A20M# (Mask A20) / A20GATE ............................................. 168
5.12.1.2 INIT (Initialization).............................................................. 169
5.12.1.3 FERR# (Numeric Coprocessor Error) ...................................... 169
5.12.1.4 NMI (Non-Maskable Interrupt) .............................................. 170
5.12.1.5 Processor Power Good (PROCPWRGD) .................................... 170
5.12.2 Dual-Processor Issues........................................................................ 170
5.12.2.1 Usage Differences ............................................................... 170
5.12.3 Virtual Legacy Wire (VLW) Messages.................................................... 170
Power Management (D31:F0) ........................................................................... 171
5.13.1 Features .......................................................................................... 171
5.13.2 PCH and System Power States ............................................................ 171
5.13.3 System Power Planes......................................................................... 173
5.13.4 SMI#/SCI Generation ........................................................................ 173
5.13.4.1 PCI Express* SCI ................................................................ 176
5.13.4.2 PCI Express* Hot-Plug ......................................................... 176
5.13.5 C-States .......................................................................................... 176
5.13.6 Dynamic PCI Clock Control (Mobile Only).............................................. 176
5.13.6.1 Conditions for Checking the PCI Clock .................................... 177
5.13.6.2 Conditions for Maintaining the PCI Clock................................. 177
5.13.6.3 Conditions for Stopping the PCI Clock .................................... 177
5.13.6.4 Conditions for Re-Starting the PCI Clock................................. 177
Datasheet
5

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3400 arduino
11.1.14
11.1.15
11.1.16
11.1.17
11.1.18
11.1.19
11.1.20
11.1.21
11.1.22
11.1.23
11.1.24
11.1.25
PREF_MEM_BASE_LIMIT—Prefetchable Memory Base
and Limit Register (PCI-PCI—D30:F0) .................................................. 443
PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI-PCI—D30:F0) ................................................................ 444
PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI-PCI—D30:F0) ................................................................ 444
CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) ....................... 444
INTR—Interrupt Information Register (PCI-PCI—D30:F0)........................ 444
BCTRL—Bridge Control Register (PCI-PCI—D30:F0) ............................... 445
SPDH—Secondary PCI Device Hiding Register
(PCI-PCI—D30:F0) ............................................................................ 447
DTC—Delayed Transaction Control Register
(PCI-PCI—D30:F0) ............................................................................ 447
BPS—Bridge Proprietary Status Register
(PCI-PCI—D30:F0) ............................................................................ 449
BPC—Bridge Policy Configuration Register
(PCI-PCI—D30:F0) ............................................................................ 450
SVCAP—Subsystem Vendor Capability Register
(PCI-PCI—D30:F0) ............................................................................ 451
SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0) ..................... 451
12 Gigabit LAN Configuration Registers ...................................................................... 453
12.1 Gigabit LAN Configuration Registers
(Gigabit LAN—D25:F0)..................................................................................... 453
12.1.1 VID—Vendor Identification Register
(Gigabit LAN—D25:F0)....................................................................... 454
12.1.2 DID—Device Identification Register
(Gigabit LAN—D25:F0)....................................................................... 454
12.1.3 PCICMD—PCI Command Register
(Gigabit LAN—D25:F0)....................................................................... 455
12.1.4 PCISTS—PCI Status Register
(Gigabit LAN—D25:F0)....................................................................... 456
12.1.5 RID—Revision Identification Register
(Gigabit LAN—D25:F0)....................................................................... 457
12.1.6 CC—Class Code Register
(Gigabit LAN—D25:F0)....................................................................... 457
12.1.7 CLS—Cache Line Size Register
(Gigabit LAN—D25:F0)....................................................................... 457
12.1.8 PLT—Primary Latency Timer Register
(Gigabit LAN—D25:F0)....................................................................... 457
12.1.9 HT—Header Type Register
(Gigabit LAN—D25:F0)....................................................................... 457
12.1.10 MBARA—Memory Base Address Register A
(Gigabit LAN—D25:F0)....................................................................... 458
12.1.11 MBARB—Memory Base Address Register B
(Gigabit LAN—D25:F0)....................................................................... 458
12.1.12 MBARC—Memory Base Address Register C
(Gigabit LAN—D25:F0)....................................................................... 459
12.1.13 SVID—Subsystem Vendor ID Register
(Gigabit LAN—D25:F0)....................................................................... 459
12.1.14 SID—Subsystem ID Register
(Gigabit LAN—D25:F0)....................................................................... 459
12.1.15 ERBA—Expansion ROM Base Address Register
(Gigabit LAN—D25:F0)....................................................................... 459
12.1.16 CAPP—Capabilities List Pointer Register
(Gigabit LAN—D25:F0)....................................................................... 460
12.1.17 INTR—Interrupt Information Register
(Gigabit LAN—D25:F0)....................................................................... 460
12.1.18 MLMG—Maximum Latency/Minimum Grant Register
(Gigabit LAN—D25:F0)....................................................................... 460
12.1.19 CLIST 1—Capabilities List Register 1
(Gigabit LAN—D25:F0)....................................................................... 460
12.1.20 PMC—PCI Power Management Capabilities Register
(Gigabit LAN—D25:F0)....................................................................... 461
12.1.21 PMCS—PCI Power Management Control and Status
Register (Gigabit LAN—D25:F0) .......................................................... 462
Datasheet
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