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PDF MC34084DW Data sheet ( Hoja de datos )

Número de pieza MC34084DW
Descripción HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo



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t
High Slew Rate, Wide
Bandwidth, JFET Input
Operational Amplifiers
These devices are a new generation of high speed JFET input monolithic
operational amplifiers. Innovative design concepts along with JFET
technology provide wide gain bandwidth product and high slew rate.
Well–matched JFET input devices and advanced trim techniques ensure low
input offset errors and bias currents. The all NPN output stage features large
output voltage swing, no deadband crossover distortion, high capacitive
drive capability, excellent phase and gain margins, low open loop output
impedance, and symmetrical source/sink AC frequency response.
This series of devices is available in fully compensated or
decompensated (AVCL2) and is specified over a commercial temperature
range. They are pin compatible with existing Industry standard operational
amplifiers, and allow the designer to easily upgrade the performance of
existing designs.
Wide Gain Bandwidth: 8.0 MHz for Fully Compensated Devices
Wide Gain Bandwidth: 16 MHz for Decompensated Devices
High Slew Rate: 25 V/µs for Fully Compensated Devices
High Slew Rate: 50 V/µs for Decompensated Devices
High Input Impedance: 1012
Input Offset Voltage: 0.5 mV Maximum (Single Amplifier)
Large Output Voltage Swing: –14.7 V to +14 V for
Large Output Voltage Swing: VCC/VEE = ±15 V
Low Open Loop Output Impedance: 30 @ 1.0 MHz
Low THD Distortion: 0.01%
Excellent Phase/Gain Margins: 55°/7.6 dB for Fully Compensated
Devices
Op Amp
Function
Single
Dual
Quad
ORDERING INFORMATION
Fully
Compen-
sated
AVCL2
Compensated
Operating
Temperature
Range
MC34081BD MC34080BD
MC34081BP
MC34082P
MC34080BP
MC34083BP
TA = 0° to +70°C
MC34084DW MC34085BDW
MC34084P MC34085BP
TA = 0° to +70°C
Package
SO–8
Plastic DIP
Plastic DIP
SO–16L
Plastic DIP
Output 1 1
2
Inputs 1
3+1
VCC 4
5
Inputs 2
6
+
–2
Output 2 7
NC 8
16 Output 4
4+
15
14
Inputs 4
13 VEE
+ 12
3 – 11
Inputs 3
10 Output 3
9 NC
PIN CONNECTIONS
Order this document by MC34080/D
MC34080
thru
MC34085
HIGH PERFORMANCE
JFET INPUT
OPERATIONAL AMPLIFIERS
8
1
P SUFFIX
PLASTIC PACKAGE
CASE 626
8
1
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
PIN CONNECTIONS
Offset Null 1
8 NC
Inv. Input 2 –
Noninv. Input 3 +
7 VCC
6 Output
VEE 4
5 Offset Null
(Single, Top View)
Output 1 1
2
Inputs 1
3+
VEE 4
8 VCC
7 Output 2
6
+5
Inputs 2
(Dual, Top View)
14
1
P SUFFIX
PLASTIC PACKAGE
CASE 646
16
1
DW SUFFIX
PLASTIC PACKAGE
CASE 751G
(SO–16L)
Output 1 1
2
Inputs 1
3+1
VCC 4
Inputs 2 5 +
6–2
Output 2 7
14 Output 4
13
4 + 12
Inputs 4
11 VEE
+ 10
3– 9
Inputs 3
8 Output 3
(Quad, Top View)
MOTOROLA ANALOG IC DEVICE DATA
© Motorola, Inc. 1996
Rev 0
1

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MC34084DW pdf
MC34080 thru MC34085
Figure 3. Input Bias Current versus
Input Common Mode Voltage
140
120
VCC/VEE = ±15 V
TA = 25°C
100
80
60
40
20
–12
–8.0 –4.0 0 4.0 8.0
VIC, INPUT COMMON MODE VOLTAGE (V)
12
Figure 4. Output Voltage Swing
versus Supply Voltage
50
40
RL Connected to Ground
TA = 25°C
30
RL = 10 k
20
RL = 2.0 k
10
0
0 ±5.0 ±10 ±15 ±20
VCC |VEE|, SUPPLY VOLTAGE (V)
±25
Figure 5. Output Saturation versus
Load Current
0
VCC
–1.0
Source
–2.0
VCC/VEE = +15 V to +22 V
TA = 25°C
–3.0
1.0 Sink
VEE
0
0 4.0 8.0 12
IL, LOAD CURRENT (±mA)
16
Figure 6. Output Saturation vesus
Load Resistance to Ground
0
VCC
–2.0
–4.0
VCC/VEE = ±15 V
TA = 25°C
2.0
1.0
0
300
VEE
3.0 k 30 k
RL, LOAD RESISTANCE TO GROUND ()
300 k
Figure 7. Output Saturation versus
Load Resistance to VCC
0
VCC
–0.4
–0.8
2.0
1.0
0
300
VCC/VEE = +15 V
RL to VCC
TA = 25°C
VEE
3.0 k 30 k
RL, LOAD RESISTANCE TO VCC ()
300 k
Figure 8. Output Short Circuit Current
versus Temperature
40
30 Source
Sink
20
10
0
–55
VCC/VEE = ±15 V
RL 0.1
Vin = 1.0 V
–25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
MOTOROLA ANALOG IC DEVICE DATA
5

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MC34084DW arduino
MC34080 thru MC34085
APPLICATIONS INFORMATION
The bandwidth and slew rate of the MC34080 series is
nearly double that of currently available general purpose
JFET op–amps. This improvement in AC performance is due
to the P–channel JFET differential input stage driving a
compensated miller integration amplifier in conjunction with
an all NPN output stage.
The all NPN output stage offers unique advantages over
the more conventional NPN/PNP transistor Class AB output
stage. With a 10 k load resistance, the op amp can typically
swing within 1.0 V of the positive rail (VCC), and within 0.3 V
of the negative rail (VEE), providing a 28.7 p–p swing from
±15 V supplies. This large output swing becomes most
noticeable at lower supply voltages. If the load resistance is
referenced to VCC instead of ground, the maximum possible
output swing can be achieved for a given supply voltage. For
light load currents, the load resistance will pull the output to
VCC during the positive swing and the NPN output transistor
will pull the output very near VEE during the negative swing.
The load resistance value should be much less than that of
the feedback resistance to maximize pull–up capability.
The all NPN transistor output stage is also inherently
fast, contributing to the operation amplifier’s high
gain–bandwidth product and fast settling time. The
associated high frequency output impedance is 50 (typical)
at 8.0 MHz. This allows driving capacitive loads from 0 pF to
300 pF without oscillations over the military temperature
range, and over the full range of output swing. The 55°C
phase margin and 7.6 dB gain margin as well as the general
gain and phase characteristics are virtually independent of
the sink/source output swing conditions. The high frequency
characteristics of the MC34080 series is especially useful for
active filter applications.
The common mode input range is from 2.0 V below the
positive rail (VCC) to 4.0 V above the negative rail (VEE). The
amplifier remains active if the inputs are biased at the positive
rail. This may be useful for some applications in that single
supply operation is possible with a single negative supply.
However, a degradation of offset voltage and voltage gain
may result.
Phase reversal does not occur if either the inverting or
noninverting input (or both) exceeds the positive common
mode limit. If either input (or both) exceeds the negative
common mode limit, the output will be in the high state. The
input stage also allows a differential up to ±44 V, provided the
maximum input voltage range is not exceeded. The supply
voltage operating range is from ±5.0 V to ±22 V.
For optimum frequency performance and stability, careful
component placement and printed circuit board layout should
be exercised. For example, long unshielded input or output
leads may result in unwanted input–output coupling. In order
to reduce the input capacitance, resistors connected to the
input pins should be physically close to these pins. This not
only minimizes the input pole for optimum frequency
response, but also minimizes extraneous “pickup” at
this node.
Supply decoupling with adequate capacitance close to the
supply pin is also important, particularly over temperature,
since many types of decoupling capacitors exhibit large
impedance changes over temperature.
Primarily due to the JFET inputs of the op amp, the input
offset voltage may change due to temperature cycling and
board soldering. After 20 temperature cycles (– 55° to
165°C), the typical standard deviation for input offset voltage
is 559 µV in the plastic packages. With respect to board
soldering (260°C, 10 seconds), the typical standard deviation
for input offset voltage is 525 µV in the plastic package.
Socketed devices should be used over a minimal
temperature range for optimum input offset voltage
performance.
Figure 34. Offset Nulling Circuit
VCC
3+ 7
6
2– 5
1
4
5.0 k
VEE
MOTOROLA ANALOG IC DEVICE DATA
11

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