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PDF PCA9527 Data sheet ( Hoja de datos )
| Número de pieza | PCA9527 | |
| Descripción | 3-channel bidirectional bus extender | |
| Fabricantes | NXP Semiconductors | |
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PCA9527
3-channel bidirectional bus extender for HDMI, I2C-bus and
SMBus
Rev. 01 — 29 June 2009
Product data sheet
1. General description
The PCA9527 is a 3-channel bidirectional open-drain bus buffer for Display Data Control
(DDC) clock, data and Consumer Electronic Control (CEC) for HDMI application. The
device has two power supply pins to allow voltage level shift from 2.7 V to 5 V, and a
rise time accelerator on port A of each DDC clock and data for driving longer cable (up to
18 meters or 1400 pF reliably without violating the bus rise time). The 5 V tolerant CEC
channel is internally connected to VCC(B) and has no rise time accelerator. The CEC
channel can be used as an interrupt or reset.
While retaining all the operating modes and features of the I2C-bus system during the
level shift, it also permits extension of the I2C-bus by providing bidirectional buffering for
data (SDA), clock (SCL), and CEC. Using the PCA9527 enables the system designer to
isolate bus capacitance to meet HDMI DDC version 1.3 distance specification. The SDAx
and SCLx pins are overvoltage tolerant and are high-impedance when the PCA9527 is
unpowered. The port B drivers (SDAB, SCLB, CECB) with static level offset behave much
like the drivers on the PCA9515 device, while the SDAA and SCLA drivers integrate the
rise time accelerator, sink more current and eliminate the static offset voltage. The CECA
driver has the same current and static offset voltage features as the SDAA and SCLA, but
it does not have the rise time accelerator and is powered and referenced to VCC(B). This
results in a LOW on the port B translating into a nearly 0 V LOW on port A, providing zero
offset. The static level offset design of the port B I/O drivers prevent them from being
connected to another device that has rise time accelerator including the PCA9507
(port B), PCA9510, PCA9511, PCA9512, PCA9513, PCA9514, PCA9515, PCA9516A,
PCA9517 (port B), or PCA9518A. Port A of two or more PCA9527s can be connected
together, however, to allow a star topography with port A on the common bus, and port A
can be connected directly to any other buffer with static or dynamic offset voltage. Multiple
PCA9527s can be connected in series, port A to port B, with no build-up in offset voltage
with only time of flight delays to consider. Rise time accelerators on the SDAA and SCLA
pins are turned on when input threshold is above 0.3VCC(A). The PCA9527 SDA and SCL
drivers are not enabled unless VCC(A) and VCC(B) are above 2.7 V. The EN pin can also be
used to turn the drivers on and off under system control. Caution should be observed to
only change the state of the enable pin when the bus is idle. The output pull-down on the
port B internal buffer LOW is set for approximately 0.5 V, while the input threshold of the
internal buffer is set about 70 mV lower (0.43 V). When the port B I/O is driven LOW
internally, the LOW is not recognized as a LOW by the input. This prevents a lock-up
condition from occurring.
1 page  
NXP Semiconductors
PCA9527
3-channel bidirectional bus extender for HDMI, I2C-bus and SMBus
crosses the port A threshold ~0.3VCC(A) the port B driver is turned off and the rising edge
accelerator is turned on, which causes a faster rising edge until it reaches the turn-off
point for the rising edge accelerator ~0.7VCC(A). Then it continues to rise at the slower rate
determined by the RC of port A. When the port B driver turns off, port B rises with the RC
of port B.
VCC(A) powers the 0.3VCC(A) reference for SCLA and SDAA as well as the port A power
good detect circuit. VCC(B) powers the rest of the chip including the port B I/Os, the CEC
I/Os, and the support functions. Figure 3 illustrates the threshold and I/O levels for port A
and port B.
6.1 Enable
The EN pin is active HIGH with an internal ~100 kΩ pull-up to VCC(B) and allows the user
to select when the buffer is active. The enable pin puts the PCA9527 in a power-down
state when it is disabled, so that there is a recovery delay and a lower power-down power.
This can be used to isolate the line when the HDMI DDC transmitter or receiver is not
ready, or from a badly behaved slave on power-up until after the system power-up reset. It
should never change state during an I2C-bus operation because disabling during a bus
operation will hang the bus and enabling part way through a bus cycle could confuse the
I2C-bus parts being enabled. The enable pin should only change state when the global
bus and the buffer port are in an idle state to prevent system failures.
6.2 Rise time accelerators
PCA9527 has rise time accelerators on port A of SCL and SDA only; the CECA pin does
not have a rise time accelerator. During port A positive bus transitions a current source is
switched on to quickly slew the SDAA and SCLA lines HIGH once the input level of
0.3VCC(A) is exceeded for the PCA9527 and turns off as the 0.7VCC(A) voltage is
approached.
6.3 Resistor pull-up value selection
6.3.1 Port A (SDAA and SCLA)
SDAA and SCLA are open-drain I/O that have rise time accelerators and strong pull-down.
When the inputs transition above 0.3VCC(A), the rise time accelerator activates and boosts
the pull-up current during rising edge to meet the I2C-bus rise time specification when the
device drives a long cable or heavier capacitance load. The strong pull-down enables the
output to drive to nearly zero voltage for logic LOW. The selection for pull-up resistors are
defined in the HDMI DDC specification shown in Table 3. For HDMI transmitter
applications like digital video player, recorder, or set-top box, the pull-up resistor is in the
range of 1.5 kΩ to 2 kΩ. For HDMI receiver applications like in LCD TV or video card, the
pull-up resistor is 47 kΩ on the SCLA line, and there is no pull-up on the SDAA line.
Please refer to Table 3, Figure 6 and Figure 7 for more details. Figure 4 shows the port A
pull-up resistor values (in kΩ) versus capacitance load (in nF) for 5 V supply voltage
complied with 1 µs rise time per I2C-bus Standard-mode specification. The graph
contrasts a shaded and unshaded region. Any resistor value chosen within the unshaded
region would comply with 1 µs rise time, while any value chosen in the shaded region
would not.
PCA9527_1
Product data sheet
Rev. 01 — 29 June 2009
© NXP B.V. 2009. All rights reserved.
5 of 22
5 Page 
NXP Semiconductors
PCA9527
3-channel bidirectional bus extender for HDMI, I2C-bus and SMBus
CARD 2
CARD 1
VCC(A)
VCCB
RPU
RPU
75 Ω
75 Ω
75 Ω
10 kΩ
VCC(A) VCC(B)
10 kΩ
10 kΩ
(optional)
SDAA
SCLA
CECA
GND
SDAB
SCLB
CECB
EN
INT or RESET
MASTER
OR
SLAVE
Fig 10. Typical application of PCA9527 driving a short cable
002aad976
SCLA
SDAA
9th clock pulse
acknowledge
Fig 11. Bus A (2.7 V to 5.5 V bus) waveform
002aad431
SCLB
SDAB
9th clock pulse
acknowledge
VOL of slave
Fig 12. Bus B (2.7 V to 5.5 V) waveform
VOL of PCA9527
002aad977
PCA9527_1
Product data sheet
Rev. 01 — 29 June 2009
© NXP B.V. 2009. All rights reserved.
11 of 22
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