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PDF GAL26CV12C-10LJI Data sheet ( Hoja de datos )

Número de pieza GAL26CV12C-10LJI
Descripción High Performance E2CMOS PLD Generic Array Logic
Fabricantes Lattice Semiconductor 
Logotipo Lattice Semiconductor Logotipo



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No Preview Available ! GAL26CV12C-10LJI Hoja de datos, Descripción, Manual

GAL26CV12
High Performance E2CMOS PLD
Generic Array Logic™
Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 142.8 MHz
— 4.5ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS® Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
— 90 mA Typical Icc
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TWELVE OUTPUT LOGIC MACROCELLS
— Uses Standard 22V10 Macrocells
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
The GAL26CV12, at 7.5 ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E2) floating gate technology to provide the highest
performance 28-pin PLD available on the market. E2 technology
offers high speed (<100ms) erase times, providing the ability to
reprogram or reconfigure the device quickly and efficiently.
Expanding upon the industry standard 22V10 architecture, the
GAL26CV12 eliminates the learning curve typically associated with
using a new device architecture. The generic architecture provides
maximum design flexibility by allowing the Output Logic Macrocell
(OLMC) to be configured by the user. The GAL26CV12 OLMC is
fully compatible with the OLMC in standard bipolar and CMOS
22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers100% field programmability and functionality
of all GAL products. In addition, 100 erase/write cycles and data
retention in excess of 20 years are specified.
Functional Block Diagram
I/CLK
I
I
I
I
I
I
I
I
I
I
I
I
RESET
8
OLMC
8
OLMC
8
OLMC
8
OLMC
10
OLMC
12
OLMC
12
OLMC
10
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
PRESET
INPUT
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Pin Configuration
PLCC
4 2 28 26
I5
25 I/O/Q
I I/O/Q
VCC 7 GAL26CV12 23 I/O/Q
I I/O/Q
I 9 Top View 21 GND
I I/O/Q
I 11
12
14
16
19
18
I/O/Q
DIP
I/CLK
I
I
I
I
I
Vcc
I
I
I
I
I
I
I
1 28 I
I/O/Q
I/O/Q
GAL
26CV12
I/O/Q
I/O/Q
I/O/Q
7 I/O/Q
21 GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
14 15 I/O/Q
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2000
26cv12_03
1

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GAL26CV12C-10LJI pdf
Specifications GAL26CV12
GAL26CV12 Logic Diagram/JEDEC Fuse Map
DIP & PLCC Package Pinouts
1
0 4 8 12 16 20 24 28 32 36 40 44 48
0000
0052
.
.
.
0468
2
0520
.
.
.
0936
3
0988
.
.
.
1404
4
1456
.
.
.
1872
5
1924
.
.
.
.
2444
6
2496
.
.
.
.
.
3120
8
3172
.
.
.
.
.
3796
9
3848
.
.
.
.
4368
10
4420
.
.
.
4836
11
4888
.
.
.
5304
12
5356
.
.
.
5772
13
5824
.
.
.
6240
14
6292
6368, 6369 ... Electronic Signature ... 6430, 6431
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
ML
SS
BB
28
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
8 OLMC
S0
6344
S1
6345
27
8 OLMC
S0
6346
S1
6347
26
8 OLMC
S0
6348
S1
6349
25
8 OLMC
S0
6350
S1
6351
24
10 OLMC
S0
6352
S1
6353
23
12
OLMC
S0
6354
S1
6355
22
12
OLMC
S0
6356
S1
6357
20
10 OLMC
S0
6358
S1
6359
19
8 OLMC
S0
6360
S1
6361
18
8 OLMC
S0
6362
S1
6363
17
8 OLMC
S0
6364
S1
6365
16
8 OLMC
S0
6366
S1
6367
15
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
5

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GAL26CV12C-10LJI arduino
fmax Definitions
CLK
LOGIC
ARRAY
REGISTER
tsu tco
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
CLK
LOGIC
ARRAY
REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
Switching Test Conditions
Input Pulse Levels
Input Rise and
C-7/-10/-15
Fall Times
B-10/-15/-20
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5ns 10% 90%
3ns 10% 90%
1.5V
1.5V
See Figure
3-state levels are measured 0.5V from steady-state active
level.
GAL26CV12 Output Load Conditions (see figure)
Test Condition
R1 R2 CL
A
B Active High
Active Low
C Active High
Active Low
300
300
300
390
390
390
390
390
50pF
50pF
50pF
5pF
5pF
Specifications GAL26CV12
LOGIC
ARRAY
CLK
REGISTER
t cf
t pd
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
+5V
R1
FROM OUTPUT (O/Q)
UNDER TEST
R2
TEST POINT
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
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