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PDF 12F617 Data sheet ( Hoja de datos )
| Número de pieza | 12F617 | |
| Descripción | PIC12F617 | |
| Fabricantes | Microchip Technology | |
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Hay una vista previa y un enlace de descarga de 12F617 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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PIC12F609/615/617
PIC12HV609/615
Data Sheet
8-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
2010 Microchip Technology Inc.
DS41302D
1 page  
PIC12F609/615/617/12HV609/615
8-Pin Diagram, PIC12F615/617/HV615 (PDIP, SOIC, MSOP, DFN)
VDD
GP5/T1CKI/P1A*/OSC1/CLKIN
GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT
GP3/T1G*/MCLR/VPP
18
2 PIC12F615/ 7
3 617/HV615 6
45
VSS
GP0/AN0/CIN+/P1B/ICSPDAT
GP1/AN1/CIN0-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1/P1A
* Alternate pin function.
TABLE 2: PIC12F615/617/HV615 PIN SUMMARY (PDIP, SOIC, MSOP, DFN)
I/O
Pin
Analog
Comparator
s
Timer
CCP
Interrupts Pull-ups
GP0
GP1
GP2
GP3(1)
7
6
5
4
AN0
AN1
AN2
—
CIN+
CIN0-
COUT
—
—
—
T0CKI
T1G*
P1B
—
CCP1/P1A
—
IOC
IOC
INT/IOC
IOC
Y
Y
Y
Y(2)
GP4
3
AN3
CIN1- T1G P1B*
IOC
Y
GP5
2
—
—
T1CKI
P1A*
IOC
Y
—1
—
— — — ——
—8
—
— — — ——
* Alternate pin function.
Note 1: Input only.
2: Only when pin is configured for external MCLR.
Basic
ICSPDAT
ICSPCLK/VREF
—
MCLR/VPP
OSC2/CLKOUT
OSC1/CLKIN
VDD
VSS
2010 Microchip Technology Inc.
DS41302D-page 5
5 Page 
PIC12F609/615/617/12HV609/615
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC12F609/615/617/12HV609/615 has a 13-bit
program counter capable of addressing an 8K x 14
program memory space. Only the first 1K x 14 (0000h-
03FFh) for the PIC12F609/615/12HV609/615 is
physically implemented. For the PIC12F617, the first
2K x 14 (0000h-07FFh) is physically implemented.
Accessing a location above these boundaries will
cause a wrap-around within the first 1K x 14 space for
PIC12F609/615/12HV609/615 devices, and within the
first 2K x 14 space for the PIC12F617 device. The
Reset vector is at 0000h and the interrupt vector is at
0004h (see Figure 2-1).
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F609/615/12HV609/615
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector
On-chip Program
Memory
Wraps to 0000h-03FFh
0004h
0005h
03FFh
0400h
1FFFh
FIGURE 2-2:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F617
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
On-Chip
Program
Memory
Interrupt Vector
Page 0
Wraps to 0000h-07FFh
0004h
0005h
07FFh
0800h
1FFFh
2.2 Data Memory Organization
The data memory (see Figure 2-3) is partitioned into two
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 40h-7Fh in
Bank 0 are General Purpose Registers, implemented as
static RAM. For the PIC12F617, the register locations
20h-7Fh in Bank 0 and A0h-EFh in Bank 1 are general
purpose registers implemented as Static RAM. Register
locations F0h-FFh in Bank 1 point to addresses 70h-7Fh
in Bank 0. All other RAM is unimplemented and returns
‘0’ when read. The RP0 bit of the STATUS register is the
bank select bit.
RP0
0 Bank 0 is selected
1 Bank 1 is selected
Note:
The IRP and RP1 bits of the STATUS
register are reserved and should always be
maintained as ‘0’s.
2010 Microchip Technology Inc.
DS41302D-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 12F617.PDF ] | |
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