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PDF 24C32 Data sheet ( Hoja de datos )

Número de pieza 24C32
Descripción Two-wire Serial EEPROM
Fabricantes LRC 
Logotipo LRC Logotipo



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No Preview Available ! 24C32 Hoja de datos, Descripción, Manual

LESHAN RADIO COMPANY, LTD.
32K bits (4096 X 8) / 64K bits (8192 X 8) Two-wire Serial EEPROM
Two-wire Serial EEPROM
LR 24C32/LR 24C64
Features
Two-wire Serial Interface
VCC = 1.8V to 5.5V
Bi-directional Data Transfer Protocol
Internally Organized
LR24C32, 4096 X 8 (32K bits)
LR24C64, 8192 X 8 (64K bits)
400 kHz (1.8V, 2.7V,5V) Compatibility
32-byte Page (32K/64K) Write Modes
Partial Page Writes Allowed
Self-timed Write Cycle (5 ms max)
High-reliability
1 Million Write Cycles guaranteed
Data Retention > 100 Years
Operating Temperature: -40 to +85
8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages
Pin Configuration
Ordering Infomation
LR24Cxx: PDIP8
LR24CxxD: SOP8
LR24CxxT: TSSOP8
Description
LR24C32/LR24C64 provides 32768/65536 bits of serial electrically erasable and
programmable read-only memory (EEPROM) organized as 4096 words of 8 bits each. The
device is optimized for use in many industrial and commercial applications where low-power
and low-voltage operations are essential. The LR24C32/LR24C64 is available in space-saving
8-lead PDIP, 8-lead SOP, and 8-lead TSSOP packages and is accessed via a two-wire serial
interface.
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24C32 pdf
Figure 3. Output Acknowledge
LESHAN RADIO COMPANY, LTD.
3. Device Addressing
The 32K/64K EEPROM devices all require an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 4).
The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits
as shown. This is common to all the Serial EEPROM devices.
The 32K/64K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the
same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0
pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to
float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the chip
will return to a standby state.
NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins prevent small noise
spikes from activating the device.
DATA SECURITY: The 24C32/24C64 has a hardware data protection scheme that allows the user to
write protect the entire memory when the WP pin is at VCC.
4. Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word
and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”
and the addressing device, such as a microcontroller, must terminate the write sequence with a stop
condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory.
All inputs are disabled during this write cycle and the EEPROM will not respond until the write is
complete (see Figure 5).
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24C32 arduino
Package Information
PDIP Outline Dimensions
LESHAN RADIO COMPANY, LTD.
Note:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001,
Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating
plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or
protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar
protrusions shall not exceed 0.010 (0.25 mm).
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