PDF M306V8FJFP Data sheet ( Hoja de datos )

Número de pieza	M306V8FJFP
Descripción	SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fabricantes	Renesas
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No Preview Available ! M306V8FJFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ03B0082-0131 Rev.1.31 Apr 18, 2005 DESCRIPTION The M306V8FJFP are single-chip microcomputers using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 116-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. They also feature a built-in OSD display function and data slicer, making them ideal for closed caption and ID1 for TV control. Applications TV ------Table of Contents------ DESCRIPTION .................................................. 1 Central Processing Unit (CPU) .......................... 9 Reset ................................................................ 22 Processor Mode ............................................... 28 Clock Generating Circuit .................................. 50 Protection ......................................................... 67 Interrupts .......................................................... 68 Watchdog Timer ............................................... 89 DMAC .............................................................. 91 Timer .............................................................. 101 Serial I/O ........................................................ 123 A/D Converter ................................................ 156 Multi-master I2C-BUS Interface ..................... 170 Data Slicer ..................................................... 190 HSYNC Counter ............................................. 203 OSD Functions ............................................... 204 Programmable I/O Ports ................................ 260 ELECTRICAL CHARACTERISTICS .............. 295 Flash Memory Version ................................... 316 Usage Precaution .......................................... 348 PACKAGE OUTLINE ..................................... 363 Rev.1.31 Apr 18, 2005 page 1 of 363 REJ03B0082-0131 1 page M306V8FJFP Pin Configuration Figures 1.3 show the pin configuration. PIN CONFIGURATION (top view) P07/AN07/D7 P06/AN06/D6 P05/AN05/D5 P04/AN04/D4 P03 / D3 P02/ D2 P01/ D1 P00/ D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5 /KI1 P104/AN4 /KI0 CAP/ P103/AN3 R/DIGR0 G/DIGG0 VSS B/DIGB0 CNVss2 VCC3 OSCOUT DIGR1 DIGG1 DIGB1 DIGR2 DIGG2 DIGB2 HSYNC CVIN1 VHOLD1 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 88 89 90 91 92 93 94 95 96 97 98 VCC1 system 99 100 101 102 103 104 105 106 107 VCC3 system 108 109 110 111 112 113 114 115 116 VCC2 system M306V8 Group VCC1 system 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 P43/A19 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0/SCL3 P61/CLK0/SDA3 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CLKS1/CTS0 P65/CLK1 P66/RxD1 /SCL1 P67/TXD1 /SDA1 SCL6 (Note 1) SDA6 (Note 1) SCL5 (Note 1) NC SDA5 (Note 1) SCL4 (Note 1) SDA4 (Note 1) Vss Package: 116P6A-A Notes 1: N channel open-drain output pins. 2: Use this MCU (microcomputer) with Vcc1 = Vcc2 = Vcc3 = 3.3V. Figure 1.3. Pin Configuration (Top View) Rev.1.31 Apr 18, 2005 page 5 of 363 REJ03B0082-0131 5 Page M306V8FJFP SFR Address 000016 000116 000216 000316 000416 Processor mode register 0 Register 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Processor mode register 1 System clock control register 0 System clock control register 1 Chip select control register Address match interrupt enable register Protect register Data bank register System clock control register 2 Watchdog timer start register Watchdog timer control register Address match interrupt register 0 Address match interrupt register 1 Reserved register Reserved register Chip select expansion control register 2 Reserved register Reserved register Reserved register DMA0 source pointer DMA0 destination pointer DMA0 transfer counter DMA0 control register DMA1 source pointer DMA1 destination pointer DMA1 transfer counter DMA1 control register Symbol After reset (Note 2) PM0 PM1 CM0 CM1 CSR AIER PRCR DBR CM2 WDTS WDC RMAD0 RMAD1 000000002(CNVSS1 pin is “L”) 000000112(CNVSS1 pin is “H”) 000010002 010010002 001000002 000000012 XXXXXX002 XX0000002 0016 0000X0002 ??16 00??????2 0016 0016 X016 0016 0016 X016 RSVREG0019 RSVREG001A CSE RSVREG001C RSVREG001E RSVREG001F SAR0 DAR0 TCR0 000010002 0016 0016 0001X0102 XXX000002 0016 ??16 ??16 X?16 ??16 ??16 X?16 ??16 ??16 DM0CON 00000?002 SAR1 DAR1 TCR1 DM1CON ??16 ??16 X?16 ??16 ??16 X?16 ??16 ??16 00000?002 Note 1: The blank areas are reserved and cannot be accessed by users. Note 2: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset. X : Nothing is mapped to this bit ? : This bit is indeterminate. Rev.1.31 Apr 18, 2005 page 11 of 363 REJ03B0082-0131 11 Page

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