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PDF EDJ1108DBSE Data sheet ( Hoja de datos )
| Número de pieza | EDJ1108DBSE | |
| Descripción | 128M words x 8 bits 1G bits DDR3 SDRAM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
1G bits DDR3 SDRAM
EDJ1108DBSE (128M words × 8 bits)
EDJ1116DBSE (64M words × 16 bits)
Specifications
• Density: 1G bits
• Organization
16M words × 8 bits × 8 banks (EDJ1108DBSE)
8M words × 16 bits × 8 banks (EDJ1116DBSE)
• Package
78-ball FBGA (EDJ1108DBSE)
96-ball FBGA (EDJ1116DBSE)
Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD, VDDQ = 1.5V ± 0.075V
• Data rate
1600Mbps/1333Mbps (max.)
• 1KB page size (EDJ1108DBSE)
Row address: A0 to A13
Column address: A0 to A9
• 2KB page size (EDJ1116DBSE)
Row address: A0 to A12
Column address: A0 to A9
• Eight internal banks for concurrent operation
• Interface: SSTL_15
• Burst lengths (BL): 8 and 4 with Burst Chop (BC)
• Burst type (BT):
Sequential (8, 4 with BC)
Interleave (8, 4 with BC)
• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
• /CAS Write Latency (CWL): 5, 6, 7, 8
• Precharge: auto precharge option for each burst
access
• Driver strength: RZQ/7, RZQ/6, RZQ/5 (RZQ = 240Ω)
• Refresh: auto-refresh, self-refresh
• Refresh cycles
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
• Multi Purpose Register (MPR) for temperature read
out
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• /RESET pin for Power-up sequence and reset
function
• SRT range:
Normal/extended
• Programmable Output driver impedance control
• Seamless BL4 access with bank-grouping
Document No. E1463E40 (Ver. 4.0)
Date Published December 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2009
1 page  
EDJ1108DBSE, EDJ1116DBSE
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations (×8 configuration) ............................................................................................................3
Pin Configurations (×16 configuration) ..........................................................................................................4
Electrical Conditions ......................................................................................................................................7
Absolute Maximum Ratings .......................................................................................................................... 7
Operating Temperature Condition ................................................................................................................ 7
Recommended DC Operating Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................... 8
AC and DC Input Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)....................... 8
VREF Tolerances ......................................................................................................................................... 9
Input Slew Rate Derating ............................................................................................................................ 10
AC and DC Logic Input Levels for Differential Signals ................................................................................ 15
AC and DC Output Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) .................. 20
AC Overshoot/Undershoot Specification..................................................................................................... 22
Output Driver Impedance............................................................................................................................ 23
On-Die Termination (ODT) Levels and I-V Characteristics ......................................................................... 25
ODT Timing Definitions............................................................................................................................... 27
IDD Measurement Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................................... 31
Electrical Specifications...............................................................................................................................44
DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................................................. 44
DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................................................. 45
Pin Capacitance (TC = 25°C, VDD, VDDQ = 1.5V ± 0.075V) ..................................................................... 46
Standard Speed Bins .................................................................................................................................. 47
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V, VSS, VSSQ = 0V)....................... 49
Block Diagram .............................................................................................................................................57
Pin Function.................................................................................................................................................58
Command Operation ...................................................................................................................................60
Command Truth Table ................................................................................................................................ 60
CKE Truth Table ......................................................................................................................................... 65
Simplified State Diagram .............................................................................................................................66
RESET and Initialization Procedure ............................................................................................................66
Power-Up and Initialization Sequence ........................................................................................................ 66
Reset and Initialization with Stable Power .................................................................................................. 67
Programming the Mode Register.................................................................................................................68
Mode Register Set Command Cycle Time (tMRD) ..................................................................................... 68
MRS Command to Non-MRS Command Delay (tMOD) ............................................................................. 68
DDR3 SDRAM Mode Register 0 [MR0] ...................................................................................................... 69
Data Sheet E1463E40 (Ver. 4.0)
5
5 Page 
EDJ1108DBSE, EDJ1116DBSE
[Derating Values of tIS/tIH AC/DC based AC175 Threshold (DDR3-1333, 1600)]
∆tIS, ∆tIH derating in [ps] AC/DC based
AC175 Threshold -> VIH(AC)=VREF(DC)+175mV, VIL(AC)=VREF(DC)-175mV
CK, /CK differential slew rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH Unit
2.0 +88 +50 +88 +50 +88 +50 +96 +58 +104 +66 +112 +74 +120 +84 +128 +100 ps
1.5 +59 +34 +59 +34 +59 +34 +67 +42 +75 +50 +83 +58 +91 +68 +99 +84 ps
1.0 0 0 0 0 0 0 +8
CMD,
ADD 0.9 −2 −4 −2 −4 −2 −4 +6
slew 0.8 −6 −10 −6 −10 −6 −10 +2
rate
(V/ns) 0.7 −11 −16 −11 −16 −11 −16 −3
0.6 −17 −26 −17 −26 −17 −26 −9
+8 +16 +16 +24 +24 +32 +34 +40 +50 ps
+4 +14 +12 +22 +20 +30 +30 +38 +46 ps
−2 +10 +6 +18 +14 +26 +24 +34 +40 ps
−8 +5 0
+13 +8 +21 +18 +29 +34 ps
−18 −1 −10 +7 −2 +15 +8 +23 +24 ps
0.5 −35 −40 −35 −40 −35 −40 −27 −32 −19 −24 −11 −16 −2 −6 +5 +10 ps
0.4 −62 −60 −62 −60 −62 −60 −54 −52 −46 −44 −38 −36 −30 −26 −22 −10 ps
[Derating Values of tIS/tIH AC/DC based-Alternate AC150 Threshold (DDR3-1333, 1600)]
∆tIS, ∆tIH derating in [ps] AC/DC based
Alternate AC150 Threshold -> VIH(AC)=VREF(DC)+150mV, VIL(AC)=VREF(DC)-150mV
CK, /CK differential slew rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH Unit
2.0 +75 +50 +75 +50 +75 +50 +83 +58 +91 +66 +99 +74 +107 +84 +115 +100 ps
1.5 +50 +34 +50 +34 +50 +34 +58 +42 +66 +50 +74 +58 +82 +68 +90 +84 ps
1.0
CMD,
ADD 0.9
slew 0.8
rate
(V/ns) 0.7
0.6
0
0
0
0
−1
00
−4 0
−10 0
−16 0
−26 −1
00
−4 0
−10 0
−16 0
−26 −1
0 +8
−4 +8
−10 +8
−16 +8
−26 +7
+8 +16 +16 +24 +24 +32 +34 +40 +50 ps
+4 +16 +12 +24 +20 +32 +30 +40 +46 ps
−2 +16 +6 +24 +14 +32 +24 +40 +40 ps
−8 +16 0
+24 +8 +32 +18 +40 +34 ps
−18 +15 −10 +23 −2 +31 +8 +39 +24 ps
0.5 −10 −40 −10 −40 −10 −40 −2 −32 +6 −24 +14 −16 +22 −6 +30 +10 ps
0.4 −25 −60 −25 −60 −25 −60 −17 −52 −9 −44 −1 −36 +7 −26 +15 −10 ps
[Required time tVAC above VIH(AC) {below VIL(AC)} for Valid Transition]
tVAC @ AC175 [ps]
tVAC @ AC150 [ps]
Slew rate (V/ns)
min.
max.
min.
max.
>2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
<0.5
75
57
50
38
34
29
22
13
0
0
175
170
167
163
162
161
159
155
150
150
Data Sheet E1463E40 (Ver. 4.0)
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EDJ1108DBSE.PDF ] | |
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