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PDF GAL20XV10B-20LP Data sheet ( Hoja de datos )

Número de pieza GAL20XV10B-20LP
Descripción High-Speed E2CMOS PLD Generic Array Logic
Fabricantes Lattice Semiconductor 
Logotipo Lattice Semiconductor Logotipo



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No Preview Available ! GAL20XV10B-20LP Hoja de datos, Descripción, Manual

GAL20XV10
High-Speed E2CMOS PLD
Generic Array Logic™
Features
HIGH PERFORMANCE E2CMOS ® TECHNOLOGY
10 ns Maximum Propagation Delay
Fmax = 100 MHz
7 ns Maximum from Clock Input to Data Output
TTL Compatible 16 mA Outputs
UltraMOS® Advanced CMOS Technology
50% to 75% REDUCTION IN POWER FROM BIPOLAR
90mA Maximum Icc
75mA Typical Icc
ACTIVE PULL-UPS ON ALL PINS
E2 CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/100% Yields
High Speed Electrical Erasure (<100 ms)
20 Year Data Retention
TEN OUTPUT LOGIC MACROCELLS
XOR Gate Capability on all Outputs
Full Function and Parametric Compatibility with
PAL12L10, 20L10, 20X10, 20X8, 20X4
Registered or Combinatorial with Polarity
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
APPLICATIONS INCLUDE:
High Speed Counters
Graphics Processing
Comparators
ELECTRONIC SIGNATURE FOR IDENTIFICATION
Functional Block Diagram
I/CLK
I
I
I
I
I
I
I
I
I
I
4
OLMC
4
OLMC
4
OLMC
4
OLMC
4
OLMC
4
OLMC
4
OLMC
4
OLMC
4
OLMC
4
OLMC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Description
I/OE
The GAL20XV10 combines a high performance CMOS process
with electrically erasable (E2) floating gate technology to provide
the highest speed Exclusive-OR PLD available in the market. At
90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides
a substantial savings in power when compared to bipolar counter-
parts. E2CMOS technology offers high speed (<100ms) erase
times providing the ability to reprogram, reconfigure or test the de-
vices quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configu-
rations possible with the GAL20XV10 are the PAL® architectures
listed in the macrocell description section of this document. The
GAL20XV10 is capable of emulating these PAL architectures with
full function and parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
PLCC
4
I5
2 28 26
25 I/O/Q
I I/O/Q
I 7 GAL20XV10 23 I/O/Q
NC NC
I 9 Top View 21 I/O/Q
I I/O/Q
I 11
19 I/O/Q
12 14 16 18
DIP
I/CLK 1
I
24 Vcc
I/O/Q
I I/O/Q
I GAL I/O/Q
20XV10
I I/O/Q
I6
I/O/Q
I 18 I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
GND 12
13 I/OE
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
20xv10_02
1

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GAL20XV10B-20LP pdf
Specifications GAL20XV10
Input Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2)
0 4 8 12 16 20 24 28 32 36
0
120
2(3)
3(4)
160
280
4(5)
320
440
5(6)
480
600
6(7)
640
760
7(9)
800
920
8(10)
960
1080
9(11)
1120
1240
10(12)
1280
1400
1440
1560
11(13)
40-USER ELECTRONIC SIGNATURE FUSES
1631, 1632, ....
.... 1669, 1670
Byte4 Byte3 ....
.... Byte1 Byte0
OLMC
XOR - 1600
AC0 - 1610
AC1 - 1620
OLMC
XOR - 1601
AC0 - 1611
AC1 - 1621
OLMC
XOR - 1602
AC0 - 1612
AC1 - 1622
OLMC
XOR - 1603
AC0 - 1613
AC1 - 1623
OLMC
XOR - 1604
AC0 - 1614
AC1 - 1624
OLMC
XOR - 1605
AC0 - 1615
AC1 - 1625
OLMC
XOR - 1606
AC0 - 1616
AC1 - 1626
OLMC
XOR - 1607
AC0 - 1617
AC1 - 1627
OLMC
XOR - 1608
AC0 - 1618
AC1 - 1628
OLMC
XOR - 1609
AC0 - 1619
AC1 - 1629
23(27)
22(26)
21(25)
20(24)
19(23)
18(21)
17(20)
16(19)
15(18)
14(17)
13(16)
SYN - 1630
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GAL20XV10B-20LP arduino
fmax Descriptions
CLK
Specifications GAL20XV10
LOGIC
ARRAY
REGISTER
CLK
tsu tco
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured
tsu and tco.
CLK
LOGIC
ARRAY
REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
LOGIC
ARRAY
REGISTER
t cf
t pd
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
GND to 3.0V
3ns 10% 90%
1.5V
1.5V
Output Load
See Figure
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Test Condition
A
Active High
B Active Low
Active High
C Active Low
R1
300
300
300
R2
390
390
390
390
390
CL
50pF
50pF
50pF
5pF
5pF
+5V
R1
FROM OUTPUT (O/Q)
UNDER TEST
R2
TEST POINT
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
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