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PDF M34F04 Data sheet ( Hoja de datos )

Número de pieza M34F04
Descripción 4Kbit Serial I2C Bus EEPROM
Fabricantes STMicroelectronics 
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No Preview Available ! M34F04 Hoja de datos, Descripción, Manual

M34F04
4Kbit Serial I²C Bus EEPROM
With Hardware Write Control on Top Half of Memory
FEATURES SUMMARY
Two Wire I2C Serial Interface
Supports 400 kHz Protocol
2.5 to 5.5V Single Supply Voltage:
Hardware Write Control of the top half of
memory (addresses 100h to 1FFh)
BYTE and PAGE WRITE (up to 16 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Behavior
More than 1 Million Erase/Write Cycles
More than 40 Year Data Retention
SO8 Package
– ECOPACK® (RoHS compliant)
Figure 1. Packages
SO8 (MN)
150 mil width
January 2006
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M34F04 pdf
M34F04
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor can be con-
nected from Serial Clock (SCL) to VCC. (Figure 4
indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to VCC. (Fig-
ure 4 indicates how the value of the pull-up resistor
can be calculated).
Chip Enable (E1, E2)
These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2) of the 7-bit Device Select Code. These in-
puts must be tied to VCC or VSS, to establish the
Device Select Code.
Write Control (WC)
This input signal is useful for protecting half of the
memory from inadvertent write operations. Write
operations are disabled to the upper half (1FFh to
100h) of the memory array when Write Control
(WC) is driven High. When unconnected, the sig-
nal is internally read as VIL, and Write operations
are allowed.
When attempting to write in the upper half of the
memory, while Write Control (WC) is being driven
High, Device Select and Address bytes are ac-
knowledged, Data bytes are not acknowledged.
Supply voltage (VCC)
Operating supply voltage VCC. Prior to select-
ing the memory and issuing instructions to it, a val-
id and stable VCC voltage must be applied: this
voltage must be a DC voltage within the specified
[VCC(min), VCC(max)] range as defined in Table 5.
This voltage must remain stable and valid until the
end of the transmission of the instruction and, for
a Write instruction, until the completion of the inter-
nal write cycle (tW).
Internal device reset. In order to prevent inad-
vertent Write operations during Power-up, a Pow-
er On Reset (POR) circuit is included. At Power-up
(continuous rise of VCC), the device will not re-
spond to any instruction until VCC has reached the
Power On Reset threshold voltage (this threshold
is lower than the minimum VCC operating voltage
defined in Section 9: DC and AC parameters).
When VCC has passed the POR threshold voltage,
the device is reset and in the Standby Power
mode.
Power-down. At Power-down (where VCC de-
creases continuously), as soon as VCC drops from
the normal operating voltage to below the Power
On Reset threshold voltage, the device stops re-
sponding to any instruction sent to it.
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M34F04 arduino
Figure 8. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
First byte of instruction
with RW = 0 already
decoded by the device
NO ACK
Returned
YES
Next
NO Operation is
Addressing the
Memory
ReSTART
YES
Send Address
and Receive ACK
STOP
NO START YES
Condition
M34F04
DATA for the
WRITE Operation
Continue the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
Random READ Operation
AI01847C
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (tw) is shown in Table 9,
but the typical time is shorter. To make use of this,
a polling sequence can be used by the bus master.
The sequence, as shown in Figure 8, is:
– Initial condition: a Write cycle is in progress.
– Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).
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