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PDF GAL20LV8ZD Data sheet ( Hoja de datos )
| Número de pieza | GAL20LV8ZD | |
| Descripción | Low Voltage/ Zero Power E2CMOS PLD Generic Array Logic | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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GAL20LV8ZD
Low Voltage, Zero Power E2CMOS PLD
Generic Array Logic™
Features
• 3.3V LOW VOLTAGE, ZERO POWER OPERATION
— JEDEC Compatible 3.3V Interface Standard
— Interfaces with Standard 5V TTL Devices
— 50µA Typical Standby Current (100µA Max.)
— 45mA Typical Active Current (55mA Max.)
— Dedicated Power-down Pin
• HIGH PERFORMANCE E2CMOS TECHNOLOGY
— TTL Compatible Balanced 8 mA Output Drive
— 15 ns Maximum Propagation Delay
— Fmax = 62.5 MHz
— 10 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— Ideal for Mixed 3.3V and 5V Systems
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Functional Block Diagram
I/CLK
IMUX
I CLK
8 OLMC
I
DPP
8 OLMC
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
I 8 OLMC
OE
I
IMUX
Description
The GAL20LV8ZD, at 100 µA standby current and 15ns propagation
delay provides the highest speed low-voltage PLD available in the
market. The GAL20LV8ZD is manufactured using Lattice
Semiconductor's advanced 3.3V E2CMOS process, which com-
bines CMOS with Electrically Erasable (E2) floating gate technology.
The GAL20LV8ZD utilizes a dedicated power-down pin (DPP) to
put the device into standby mode. It has 19 inputs available to the
AND array and is capable of interfacing with both 3.3V and stan-
dard 5V devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
4
DPP 5
2 28 26
25 I/O/Q
I I/O/Q
I 7 GAL20LV8ZD 23 I/O/Q
NC Top View
NC
I9
21 I/O/Q
I I/O/Q
I 11
19 I/O/Q
12 14 16 18
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/OE
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
December 1997
20lv8zd_03
1
1 page  
Specifications GAL20LV8ZD
Registered Mode Logic Diagram
PLCC Package Pinout
2
2640
0 4 8 12 16 20 24 28 32 36 PTD
3
0000
0280
4
0320
0600
5 Power
Management
Control
0640
0920
6
0960
1240
7
1280
1560
9
1600
1880
10
1920
2200
11
2240
2520
12
13
2703
64-USER ELECTRONIC SIGNATURE FUSES
2568, 2569, ....
.... 2630, 2631
Byte7 Byte6 ....
.... Byte1 Byte0
MSB
LSB
OLMC
XOR-2560
AC1-2632
27
26
OLMC
XOR-2561
AC1-2633
25
OLMC
XOR-2562
AC1-2634
24
OLMC
XOR-2563
AC1-2635
23
OLMC
XOR-2564
AC1-2636
21
OLMC
XOR-2565
AC1-2637
20
OLMC
XOR-2566
AC1-2638
19
OLMC
XOR-2567
AC1-2639
18
17
OE 16
SYN-2704
AC0-2705
5
5 Page 
Specifications GAL20LV8ZD
AC Switching Characteristics
Over Recommended Operating Conditions
TEST
PARAM COND.1
DESCRIPTION
tpd A Input or I/O to Combinatorial Output
tco A Clock to Output Delay
tcf2 — Clock to Feedback Delay
tsu — Setup Time, Input or Fdbk before Clk↑
th — Hold Time, Input or Fdbk after Clk↑
A Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
fmax3
A Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with
No Feedback
twh — Clock Pulse Duration, High
twl — Clock Pulse Duration, Low
ten B Input or I/O to Output Enabled
B OE↓ to Output Enabled
tdis C Input or I/O to Output Disabled
C OE↑ to Output Disabled
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL
CI
CI/O
PARAMETER
Input Capacitance
I/O Capacitance
TYPICAL
8
8
UNITS
pF
pF
COM
COM
-15 -25
UNITS
MIN. MAX. MIN. MAX.
3 15 3 25 ns
2 10 2 15 ns
— 8 — 10 ns
12 — 15 — ns
0 — 0 — ns
45.5 — 33.3 — MHz
50 — 40 — MHz
62.5 — 41.6 — MHz
8 — 12 —
8 — 12 —
— 17 — 25
— 16 — 20
— 18 — 25
— 17 — 20
ns
ns
ns
ns
ns
ns
TEST CONDITIONS
VCC = 3.3V, VI = 0V
VCC = 3.3V, VI/O = 0V
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet GAL20LV8ZD.PDF ] | |
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