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PDF TEA1753LT Data sheet ( Hoja de datos )
| Número de pieza | TEA1753LT | |
| Descripción | HV start-up DCM/QR flyback controller | |
| Fabricantes | NXP Semiconductors | |
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TEA1753LT
HV start-up DCM/QR flyback controller with integrated
DCM/QR PFC controller
Rev. 3 — 24 August 2012
Product data sheet
1. General description
The TEA1753LT is the third generation of green Switched Mode Power Supply (SMPS)
controller ICs. The TEA1753LT combines a controller for Power Factor Correction (PFC)
and a flyback controller. Its high level of integration allows the design of a cost-effective
power supply with a very low number of external components.
The special built-in green functions provide high efficiency at all power levels. This
efficiency applies to quasi-resonant operation at high-power levels, quasi-resonant
operation with valley skipping, as well as to reduced frequency operation at lower power
levels. At low-power levels, the PFC switches off to maintain high efficiency.
During low-power conditions, the flyback controller switches to frequency reduction mode
and limits the peak current to an adjustable minimum value. This mode ensures high
efficiency at low-power and good standby power performance while minimizing audible
noise from the transformer.
The controller can be switched to the power-down mode for no-load operation. In this
mode, the controller is shut down for very low standby power applications
The TEA1753LT is a Multi-Chip Module (MCM), containing 2 chips. The proprietary
high-voltage BCD800 process which makes direct start-up possible from the rectified
universal mains voltage in an effective and green way. The second low voltage
Silicon On Insulator (SOI) is used for accurate, high-speed protection functions and
control.
The TEA1753LT enables the design of highly efficient and reliable supplies with power
requirements of up to 250 W using a minimum number of external components.
Remark: All values provided throughout the running text, are typical values unless
otherwise stated.
1 page  
NXP Semiconductors
6. Pinning information
6.1 Pinning
TEA1753LT
HV start-up flyback controller with integrated PFC controller
VCC 1
GND 2
FBCTRL 3
FBAUX 4
LATCH 5
PFCCOMP 6
VINSENSE 7
PFCAUX 8
16 HV
15 HVS
14 PFCTIMER
13 FBDRIVER
TEA1753LT
12 PFCDRIVER
11 PFCSENSE
10 FBSENSE
9 VOSENSE
001aan785
Fig 2. Pin configuration: TEA1753LT (SOT109-1)
6.2 Pin description
Table 2. Pin description
Symbol
Pin
VCC
GND
1
2
FBCTRL
3
FBAUX
4
LATCH
5
PFCCOMP
6
VINSENSE
7
PFCAUX
8
VOSENSE
9
FBSENSE
10
PFCSENSE
11
PFCDRIVER 12
FBDRIVER
13
PFCTIMER
14
HVS
15
HV 16
Description
supply voltage
ground
flyback control input
auxiliary winding input for demagnetization timing and flyback OVP
general-purpose protection input
frequency compensation pin for PFC
mains voltage sense input
auxiliary winding input for demagnetization timing for PFC
sense input for PFC output voltage
flyback current sense input
PFC current sense input
PFC gate-driver output
flyback gate-driver output
delay timer pin for PFC on/off control
high-voltage safety spacer, not connected
high-voltage start-up/ flyback valley sensing
TEA1753LT
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 24 August 2012
© NXP B.V. 2012. All rights reserved.
5 of 32
5 Page 
NXP Semiconductors
TEA1753LT
HV start-up flyback controller with integrated PFC controller
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Fig 5. Soft-start-up of PFC
7.2.6 Low-power mode
When the output power of the flyback converter (see Section 7.3) is low, the flyback
converter switches over to frequency modulation mode. When the maximum switching
frequency of the flyback drops below 48 kHz, the power factor correction circuit is
switched off to maintain high efficiency. Connect a capacitor to the PFCTIMER pin to delay
switching off (see also Section 7.2.7).
During low-power mode operation, the PFCCOMP pin is clamped to a minimum voltage of
3.5 V or 2.5 V and a maximum voltage of 3.9 V. The lower clamp voltage depends on the
voltage on VINSENSE pin. This voltage limits the maximum power that is delivered when
the PFC is switched on again. The upper clamp voltage ensures that the PFC returns from
low-power mode to its normal regulation point in a limited time.
When the maximum switching frequency of the flyback converter exceeds 86 kHz, the
power factor correction circuit restores normal operation.
7.2.7
PFC off delay (pin PFCTIMER)
When the flyback converter maximum frequency drops below 48 kHz, the PFC is
switched off. The IC then outputs a 5 A current to the PFCTIMER pin. When the voltage
on the PFCTIMER pin reaches 3.6 V, the PFC is switched off by performing a soft-stop.
When the flyback converter frequency exceeds 86 kHz, a switch discharges the
PFCTIMER pin capacitor. When the voltage on the PCTIMER pin drops below 1.27 V, the
PFC is switched on (see Figure 6).
TEA1753LT
Product data sheet
low power
5 μA
3.6 V
1.27 V
R
Q
low power delay
S (PFC on)
14 PFCTIMER
Fig 6. PFC start/stop via PPFCTIMER pin
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 24 August 2012
014aaa740
© NXP B.V. 2012. All rights reserved.
11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TEA1753LT.PDF ] | |
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