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PDF GAL16VP8B-25LP Data sheet ( Hoja de datos )

Número de pieza GAL16VP8B-25LP
Descripción High-Speed E2CMOS PLD Generic Array Logic
Fabricantes Lattice Semiconductor 
Logotipo Lattice Semiconductor Logotipo



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GAL16VP8
High-Speed E2CMOS PLD
Generic Array Logic™
Features
HIGH DRIVE E2CMOS® GAL® DEVICE
TTL Compatible 64 mA Output Drive
15 ns Maximum Propagation Delay
Fmax = 80 MHz
10 ns Maximum from Clock Input to Data Output
UltraMOS® Advanced CMOS Technology
ENHANCED INPUT AND OUTPUT FEATURES
Schmitt Trigger Inputs
Programmable Open-Drain or Totem-Pole Outputs
Active Pull-Ups on All Inputs and I/O pins
E2 CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/100% Yields
High Speed Electrical Erasure (<100ms)
20 Year Data Retention
EIGHT OUTPUT LOGIC MACROCELLS
Maximum Flexibility for Complex Logic Designs
Programmable Output Polarity
Architecturally Compatible with Standard GAL16V8
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
100% Functional Testability
APPLICATIONS INCLUDE:
Ideal for Bus Control & Bus Arbitration Logic
Bus Address Decode Logic
Memory Address, Data and Control Circuits
DMA Control
ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
The GAL16VP8, with 64 mA drive capability and 15 ns maximum
propagation delay time is ideal for Bus and Memory control appli-
cations. The GAL16VP8 is manufactured using Lattice
Semiconductor's advanced E2CMOS process which combines
CMOS with Electrically Erasable (E2) floating gate technology. High
speed erase times (<100ms) allow the devices to be reprogrammed
quickly and efficiently.
System bus and memory interfaces require control logic before
driving the bus or memory interface signals. The GAL16VP8
combines the familiar GAL16V8 architecture with bus drivers as
its outputs. The generic architecture provides maximum design flex-
ibility by allowing the Output Logic Macrocell (OLMC) to be con-
figured by the user. The 64mA output drive eliminates the need for
additional devices to provide bus driving capability.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Functional Block Diagram
I/CLK
CLK
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
OE
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
Pin Configuration
PLCC
DIP
I/CLK 1
20 I
I
I4
I I/CLK I I/O/Q
2 20
18
I/O/Q
Vcc
I6
I
GAL16VP8
Top View
I/O/Q
16 I/O/Q
GND
I8
9
14 I/O/Q
11 13
I I/OE I/O/Q I/O/Q I/O/Q
I
I GAL
I 16VP8
Vcc 5
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I 15 GND
I I/O/Q
I I/O/Q
I I/O/Q
I/OE 10
11 I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
December 1997
16vp8_03
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GAL16VP8B-25LP pdf
Specifications GAL16VP8
Registered Mode Logic Diagram
DIP and PLCC Package Pinouts
1
2128
0 4 8 12 16 20 24 28 PTD
20
0000
0224
0256
0480
2
OLMC
XOR-2048
AC1-2120
AC2-2194
OLMC
XOR-2049
AC1-2121
AC2-2195
19
18
0512
0736
3
0768
0992
4
OLMC
XOR-2050
AC1-2122
AC2-2196
OLMC
XOR-2051
AC1-2123
AC2-2197
17
16
1024
1248
6
1280
1504
7
1536
1760
8
OLMC
XOR-2052
AC1-2124
AC2-2198
OLMC
XOR-2053
AC1-2125
AC2-2199
OLMC
XOR-2054
AC1-2126
AC2-2200
14
13
12
1792
2016
9
OLMC
11
XOR-2055
AC1-2127
AC2-2201
2191 OE 10
MSB
64-USER ELECTRONIC SIGNATURE FUSES
2056, 2055, ....
.... 2118, 2119
Byte7 Byte6 ....
.... Byte1 Byte0
LSB
SYN-2192
AC0-2193
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GAL16VP8B-25LP arduino
Specifications GAL16VP8
AC Switching Characteristics
Over Recommended Operating Conditions
TEST
PARAMETER COND1.
DESCRIPTION
tpd A Input or I/O to Combinational Output
tco A Clock to Output Delay
tcf2 Clock to Feedback Delay
tsu Setup Time, Input or Feedback before Clock
th Hold Time, Input or Feedback after Clock
A Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
COM
COM
-15 -25
UNITS
MIN. MAX. MIN. MAX.
3 15 3 25 ns
2 10 2 15 ns
4.5 10
ns
8 10 ns
0 0 ns
55.5 40 MHz
fmax3
twh
twl
ten
tdis
A Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with
No Feedback
Clock Pulse Duration, High
Clock Pulse Duration, Low
B Input or I/O to Output Enabled
B OE to Output Enabled
C Input or I/O to Output Disabled
C OE to Output Disabled
80 50 MHz
80 50 MHz
6 10
6 10
15 20
12 15
15 20
12 15
ns
ns
ns
ns
ns
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
CI Input Capacitance
CI/O I/O Capacitance
*Characterized but not 100% tested.
MAXIMUM*
10
15
UNITS
pF
pF
TEST CONDITIONS
VCC = 5.0V, VI = 2.0V
VCC = 5.0V, VI/O = 2.0V
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