|
|
PDF DAC1408D650 Data sheet ( Hoja de datos )
| Número de pieza | DAC1408D650 | |
| Descripción | Dual 14-bit DAC | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DAC1408D650 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
DAC1408D650
Dual 14-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating
with JESD204A interface
Rev. 5 — 31 January 2012
Product data sheet
1. General description
The DAC1408D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 2, 4 or 8 interpolating filters optimized for multi-carrier WCDMA
transmitters.
Because of its digital on-chip modulation, the DAC1408D650 allows the complex pattern
provided through lane 0, lane 1, lane 2 and lane 3, to be converted from baseband to IF.
The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit
Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register.
The DAC1408D650 also includes a 2, 4 or 8 clock multiplier which provides the
appropriate internal clocks and an internal regulation to adjust the output full-scale
current.
The input data format is serial according to JESD204A specification. This new interface
has numerous advantages over the traditional parallel one: easy PCB layout, lower
radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum
number of lanes of the DAC1408D650 is 4 and its maximum serial data rate is
3.125 Gbps.
The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output
clock period between several DAC devices. MDS incorporates modes: Master/slave and
All slave mode.
2. Features and benefits
Dual 14-bit resolution
650 Msps maximum update rate
Selectable 2, 4 or 8 interpolation
filters
Input data rate up to 312.5 Msps
Very low-noise cap-free integrated PLL
32-bit programmable NCO frequency
Four JESD204A serial input lanes
1.8 V and 3.3 V power supplies
LVDS compatible clock inputs
IMD3: 80 dBc; fs = 640 Msps;
fo = 140 MHz
ACPR: 71 dBc; two carriers WCDMA;
fs = 640 Msps; fo = 133 MHz
Typical 1.26 W power dissipation at 4
interpolation, PLL off and 640 Msps
Power-down mode and Sleep modes
Differential scalable output current from
1.6 mA to 22 mA
On-chip 1.29 V reference
External analog offset control
(10-bit auxiliary DACs)
Internal digital offset control
Inverse (sin x) / x function
1 page  
NXP Semiconductors
DAC1408D650
2, 4 or 8 interpolating DAC with JESD204A
DAC1408D650
Product data sheet
Table 2. Pin description …continued
Symbol
Pin Type[1] Description
AGND
12 G
analog ground
AUXBN
13 O
complementary auxiliary DAC B output
AUXBP
14 O
auxiliary DAC B output
VDDA(3V3)
AGND
15 P
16 G
analog supply voltage 3.3 V
analog ground
VDDA(1V8)
AGND
17 P
18 G
analog supply voltage 1.8 V
analog ground
VDDA(1V8)
VDDA(1V8)
AGND
19 P
20 P
21 G
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
IOUTBN
22 O
complementary DAC B output current
IOUTBP
23 O
DAC B output current
AGND
24 G
analog ground
AGND
25 G
analog ground
IOUTAP
26 O
DAC A output current
IOUTAN
27 O
complementary DAC A output current
AGND
28 G
analog ground
VDDA(1V8)
VDDA(1V8)
AGND
29 P
30 P
31 G
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
VDDA(1V8)
AGND
32 P
33 G
analog supply voltage 1.8 V
analog ground
VDDA(3V3)
AUXAP
34 P
35 O
analog supply voltage 3.3 V
auxiliary DAC A output current
AUXAN
36 O
complementary auxiliary DAC A output current
AGND
37 G
analog ground
VDDA(1V8)
VDDA(1V8)
AGND
38 P
39 P
40 G
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
CLKINP
41 I
clock input
CLKINN
42 I
complementary clock input
AGND
43 G
analog ground
VDDA(1V8)
MDS_P
44 P
45 I/O
analog supply voltage 1.8 V
multi-device synchronization
MDS_N
46 I/O
complementary multi-device synchronization
VDDD(1V8)
n.c.
47 P
48 -
digital supply voltage 1.8 V
not connected
VDDD(1V8)
SYNC_OUTN
49 P
50 O
digital supply voltage 1.8 V
synchronization request to transmitter, complementary
output
SYNC_OUTP
51 O
synchronization request to transmitter
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 31 January 2012
© NXP B.V. 2012. All rights reserved.
5 of 98
5 Page 
NXP Semiconductors
DAC1408D650
2, 4 or 8 interpolating DAC with JESD204A
Table 5. Characteristics …continued
VDDA(1V8) = VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.13 V to 3.47 V; AGND and GND are shorted together; Tamb = 40 C to
+85 C; typical values measured at VDDA(1V8) = VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 C; RL = 50 ; IO(fs) = 20 mA;
maximum sample rate; PLL off unless otherwise specified.
Symbol
Parameter
Conditions
Test[1] Min Typ Max
Unit
NSD
noise spectral density fs = 640 Msps;
4 interpolation;
fo = 133 MHz at 0 dBFS
I
- 156 -
dBm/Hz
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2] Delay between the deassertion of bits FORCE_RESET_FCLK and FORCE_RESET_DCLK and the deassertion of the sync signal. It
reflects the delay required by DAC1408D650 to lock to a JESD204A stream. It supposes that the TX is already transmitting K28.5
characters in error-free conditions.
[3] CLKINP/CLKINN inputs are at differential LVDS levels. An external termination resistor with a value of between 80 and 120 (see
Figure 15) should be connected across the pins.
[4] Vgpd represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance
and the inductance between the receiver and the driver circuit ground voltage.
[5] Vin_p and Vin_n inputs are differential CML inputs. They are terminated internally to Vtt via 50 (see Figure 4).
[6] SYNC_OUTP/SYNC_OUTN outputs are differential LVDS outputs. They must be terminated by a resistor with a value of between 80
and 120 .
[7] IMD3 rejection with 6 dBFS/tone.
10. Application information
10.1 General description
The DAC1408D650 is a dual 14-bit DAC operating up to 650 Msps. With a maximum input
data rate of up to 312.5 Msps and a maximum output sampling rate of 650 Msps, the
DAC1408D650 allows more flexibility for wide bandwidth and multi-carrier systems.
Combined with its quadrature modulator and 32-bit NCO, the DAC1408D650 simplifies
the frequency selection of the system. This is also possible because of the 2, 4 or 8
interpolation filters which remove undesired images.
DAC1408D650 supports the following JESD204A key features:
• 10-bit/8-bit decoding
• Code group synchronization
• inter-lane alignment
• 1 + x14 + x15 scrambling polynomial
• Character replacement
• TX/RX synchronization management via sync signals
• Multiple Converter Device Alignment-Multiple Lanes (MCDA-ML) device
DAC1408D650 can be interfaced with any logic device that features high speed SERDES
functionality. This macro is now widely available in FPGA from different vendors.
Standalone SERDES ICs can also be used.
To enhance the intrinsic board layout simplification of the JESD204A standard, NXP
includes polarity swapping for each of the lanes and additionally offers lane swapping.
Each physical lane can be configured logically as lane0, lane1, lane2 or lane3.
DAC1408D650
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 31 January 2012
© NXP B.V. 2012. All rights reserved.
11 of 98
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DAC1408D650.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DAC1408D650 | Dual 14-bit DAC | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |