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PDF VIPer22AS-E Data sheet ( Hoja de datos )

Número de pieza VIPer22AS-E
Descripción Low power OFF-line SMPS primary switcher
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! VIPer22AS-E Hoja de datos, Descripción, Manual

VIPer22A-E
VIPer22ADIP-E, VIPer22AS-E
Low power OFF-line SMPS primary switcher
Features
Fixed 60 kHz switching frequency
9 V to 38 V wide range VDD voltage
Current mode control
Auxiliary undervoltage lockout with hysteresis
High voltage start-up current source
Overtemperature, overcurrent and overvoltage
protection with auto-restart
Table 1. Typical power capability
Mains type
SO-8
European (195 - 265 Vac)
US / wide range (85 - 265 Vac)
12 W
7W
DIP-8
20 W
12 W
Description
The VIPer22A-E combines a dedicated current
mode PWM controller with a high voltage power
MOSFET on the same silicon chip.
Figure 1. Block diagram
SO-8
DIP-8
Typical applications cover off line power supplies
for battery charger adapters, standby power
supplies for TV or monitors, auxiliary supplies for
motor control, etc. The internal control circuit
offers the following benefits:
Large input voltage range on the VDD pin
accommodates changes in auxiliary supply
voltage. This feature is well adapted to battery
charger adapter configurations.
Automatic burst mode in low load condition.
Overvoltage protection in HICCUP mode.
DRAIN
REGULATOR
INTERNAL
SUPPLY
VDD
FB
_
8/14.5V +
+
42V _
ON/OFF
60kHz
OSCILLATOR
OVERTEMP.
DETECTOR
S
R1 FF Q
R2 R3 R4
PWM
LATCH
OVERVOLTAGE
R LATCH
S FF Q
BLANKING
+
_ 0.23 V
1 kΩ
230 Ω
SOURCE
November 2010
Doc ID 12050 Rev 2
1/21
www.st.com
21

1 page




VIPer22AS-E pdf
VIPer22A-E, VIPer22ADIP-E, VIPer22AS-E
Electrical characteristics
Table 6. Oscillation section
Symbol
Parameter
Test conditions
FOSC
Oscillator frequency
total variation
VDD = VDDoff ... 35 V;
TJ = 0 ... 100 °C
Table 7. PWM comparator section
Symbol
Parameter
Test conditions
GID
IDlim
IFBsd
RFB
td
tb
tONmin
IFB to ID current gain
Peak current
limitation
(See Figure 12 on page 14)
VFB = 0 V
(See Figure 12 on page 14)
IFB shutdown current
FB pin input
impedance
(See Figure 12 on page 14)
ID = 0 mA
(See Figure 12 on page 14)
Current sense delay
to turn-OFF
ID = 0.4 A
Blanking time
Minimum turn-ON
time
Min Typ Max Unit
54 60 66 kHz
Min Typ Max Unit
560
0.56 0.7 0.84 A
0.9 mA
1.2 kΩ
200 ns
500 ns
700 ns
Table 8.
Symbol
TSD
THYST
Overtemperature section
Parameter
Test conditions
Thermal shutdown
temperature
(See Figure 13 on page 14)
Thermal shutdown
hysteresis
(See Figure 13 on page 14)
Min Typ Max Unit
140 170
°C
40 °C
Table 9. Typical power capability (1)
Mains type
SO-8
European (195 - 265 Vac)
US / Wide range (85 - 265 Vac)
12 W
7W
1. Above power capabilities are given under adequate thermal conditions
DIP-8
20 W
12 W
Doc ID 12050 Rev 2
5/21

5 Page





VIPer22AS-E arduino
VIPer22A-E, VIPer22ADIP-E, VIPer22AS-E
4.4 Startup sequence
Figure 7. Startup sequence
Operations
This device includes a high voltage start up current source connected on the drain of the
device. As soon as a voltage is applied on the input of the converter, this start up current
source is activated as long as VDD is lower than VDDon. When reaching VDDon, the start up
current source is switched OFF and the device begins to operate by turning on and off its
main power MOSFET. As the FB pin does not receive any current from the optocoupler, the
device operates at full current capacity and the output voltage rises until reaching the
regulation point where the secondary loop begins to send a current in the optocoupler. At
this point, the converter enters a regulated operation where the FB pin receives the amount
of current needed to deliver the right power on secondary side.
This sequence is shown in Figure 7. Note that during the real starting phase tss, the device
consumes some energy from the VDD capacitor, waiting for the auxiliary winding to provide a
continuous supply. If the value of this capacitor is too low, the start up phase is terminated
before receiving any energy from the auxiliary winding and the converter never starts up.
This is illustrated also in the same figure in dashed lines.
Doc ID 12050 Rev 2
11/21

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