DataSheet.es    


PDF IS43TR85120AL Data sheet ( Hoja de datos )

Número de pieza IS43TR85120AL
Descripción 4Gb DDR3 SDRAM
Fabricantes ISSI 
Logotipo ISSI Logotipo



Hay una vista previa y un enlace de descarga de IS43TR85120AL (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! IS43TR85120AL Hoja de datos, Descripción, Manual

IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
512Mx8, 256Mx16 4Gb DDR3 SDRAM
FEATURES
Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V
- Backward compatible to 1.5V
High speed data transfer rates with system
frequency up to 1066 MHz
8 internal banks for concurrent operation
8n-Bit pre-fetch architecture
Programmable CAS Latency
Programmable Additive Latency: 0, CL-1,CL-2
Programmable CAS WRITE latency (CWL) based
on tCK
Programmable Burst Length: 4 and 8
Programmable Burst Sequence: Sequential or
Interleave
BL switch on the fly
Auto Self Refresh(ASR)
Self Refresh Temperature(SRT)
SEPTEMBER 2016
Refresh Interval:
7.8 us (8192 cycles/64 ms) Tc= -40°C to 85°C
3.9 us (8192 cycles/32 ms) Tc= 85°C to 105°C
Partial Array Self Refresh
Asynchronous RESET pin
TDQS (Termination Data Strobe) supported (x8
only)
OCD (Off-Chip Driver Impedance Adjustment)
Dynamic ODT (On-Die Termination)
Driver strength : RZQ/7, RZQ/6 (RZQ = 240 Ω)
Write Leveling
Up to 200 MHz in DLL off mode
Operating temperature:
Commercial (TC = 0°C to +95°C)
Industrial (TC = -40°C to +95°C)
Automotive, A1 (TC = -40°C to +95°C)
Automotive, A2 (TC = -40°C to +105°C)
OPTIONS
Configuration:
512Mx8
256Mx16
Package:
96-ball BGA (9mm x 13mm) for x16
78-ball BGA (9mm x 10.5mm) for x8
ADDRESS TABLE
Parameter
Row Addressing
Column Addressing
Bank Addressing
Page size
Auto Precharge
Addressing
BL switch on the fly
512Mx8
A0-A15
A0-A9
BA0-2
1KB
A10/AP
A12/BC#
256Mx16
A0-A14
A0-A9
BA0-2
2KB
A10/AP
A12/BC#
SPEED BIN
Speed Option
15H
125K
107M
JEDEC Speed Grade DDR3-1333H DDR3-1600K DDR3-1866M
CL-nRCD-nRP
9-9-9
11-11-11
13-13-13
tRCD,tRP(min)
13.5
13.75
13.91
Note:Faster speed options are backward compatible to slower speed options.
093N
DDR3-2133N
14-14-14
13.09
Units
tCK
ns
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised
to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product
can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use
in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. www.issi.com
Rev. G2
07/28/2016
1

1 page




IS43TR85120AL pdf
IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 1.5 V +/- 0.075 V for standard voltage or 1.35V +0.1V, -0.067V for low voltage
VSS
Supply
Ground
VREFDQ
Supply
Reference voltage for DQ
VREFCA
Supply
Reference voltage for CA
ZQ
Supply
Reference Pin for ZQ
Note: Input only pins (BA0-BA2, A0-A15, RAS#, CAS#, WE#, CS#, CKE, ODT, and RESET#) do not supply termination.
Integrated Silicon Solution, Inc. www.issi.com
Rev. G2
07/28/2016
5

5 Page





IS43TR85120AL arduino
IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
2.3.2 Mode Register MR0
The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length,
read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge Power-Down, which include
vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting
low on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2, while controlling the states of address pins according to the
following figure.
BA2 BA1 BA0
000
A15-A13
0* 1
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
PPD
WR
DLL TM CAS Latency RBT CL
BL Mode Register 0
A8 DLL Reset
0 No
1 Yes
A12 DLL Control for
Precharge PD
0 Slow exit (DLL off)
1 Fast exit (DLL on)
BA1 BA0
00
01
10
11
MR Select
MR0
MR1
MR2
MR3
A7 mode
A3 Read Burst Type
A1 A0
0 Nomal
0 Nibble Sequential
00
1 Test
1 Interleave
01
10
Write recovery for autoprecharge
11
A11 A10 A9
WR(cycles)
000
Reserved
A6 A5 A4 A2
001
5*2
0000
010
6*2
0010
011
7*2
0100
100
8*2
0110
101
110
10 *2
12 *2
1000
1010
111
14 *2
1100
1110
BL
8 (Fixed)
BC4 or 8 (on the fly)
BC4 (Fixed)
Reserved
CAS Latency
Reserved
5
6
7
8
9
10
11
0001
0011
0101
0111
1001
1011
1101
1111
12
13
14
Reserved
Reserved
Reserved
Reserved
Reserved
1. A15,A14 and A13 must be programmed to 0 during MRS.
2. WR (write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the next integer:
WRmin[cycles] = Roundup(tWR[ns] / tCK[ns]). The WR value in the mode register must be programmed to be equal or larger than WRmin. The
programmed WR value is used with tRP to determine tDAL.
3. The table only shows the encodings for a given Cas Latency. For actual supported Cas Latency, please refer to speedbin tables for each
frequency
4. The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timing table.
Figure 2.3.2 MR0 Definition
2.3.2.1 Burst Length, Type and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3
as shown in Figure 2.3.2. The ordering of accesses within a burst is determined by the burst length, burst type, and the
starting column address as shown in Table below. The burst length is defined by bits A0-A1. Burst length options include
fixed BC4, fixed BL8, and ‘on the fly’ which allows BC4 or BL8 to be selected coincident with the registration of a Read or
Write command via A12/BC#.
Integrated Silicon Solution, Inc. www.issi.com
Rev. G2
07/28/2016
11

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet IS43TR85120AL.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
IS43TR85120A4Gb DDR3 SDRAMISSI
ISSI
IS43TR85120AL4Gb DDR3 SDRAMISSI
ISSI

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar