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PDF LD6835K Data sheet ( Hoja de datos )
| Número de pieza | LD6835K | |
| Descripción | Low-dropout regulator | |
| Fabricantes | NXP Semiconductors | |
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LD6835 series
Low-dropout regulator, high PSRR, 300 mA
Rev. 2 — 20 September 2013
Product data sheet
1. Product profile
1.1 General description
The LD6835 series is a small-size Low-DropOut (LDO) regulator family with a high-Power
Supply Rejection Ratio (PSRR) of 75 dB and a voltage drop of 240 mV at 300 mA current
rating. Operating voltages range from 1.75 V to 5.5 V. The products are available with
fixed nominal output voltages VO(nom) between 1.2 V and 3.6 V.
The LD6835 series products are available in a DFN1010C-4 (SOT1194-1) plastic package
with a size of 1 mm 1 mm 0.55 mm. The devices are ideal for use in portable
applications requiring component miniaturization.
1.2 Features and benefits
High PSRR
Low quiescent current
Soft start with optimized start-up time
Temperature watchdog
Current limiter with foldback circuit
Low standby current in shutdown mode (typical 0.1 A)
Auto discharge or high-ohmic mode for the output state when disabled
DFN1010C-4 (SOT1194-1) plastic package with a size of 1 mm 1 mm 0.55 mm
Pb-free, Restriction of Hazardous Substances (RoHS) compliant, free of halogen and
antimony (Dark Green compliant)
1.3 Applications
Smartphones
Mobile handsets
Digital still cameras
Tablet PCs
Mobile internet devices
Portable media players
1.4 Quick reference data
IO = 300 mA
PSRR = 75 dB at 1 kHz
RMS noise Vn(o)(RMS) = 60 V
at 10 Hz to 100 kHz
tstartup(reg) = 150 s
VI = 1.75 V to 5.5 V
VO = 1.2 V to 3.6 V
Dropout voltage Vdo = 240 mV
at IO = 300 mA
Quiescent current Iq = 35 A
at IO = 0 mA
1 page  
NXP Semiconductors
LD6835 series
Low-dropout regulator, high PSRR, 300 mA
6. Recommended operating conditions
Table 6. Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb
Tj
Pin IN
ambient temperature
junction temperature
VI
Cext(IN)
Pin EN
input voltage
external capacitance on pin IN
VEN voltage on pin EN
Pin OUT
VO
CL(ext)
output voltage
external load capacitance
[1] See Section 10.1 “Capacitor values”.
7. Thermal characteristics
Min Max Unit
40 +85 C
- 125 C
1.75 5.5
1-
V
F
0.5 +5.5 V
0.5
[1] 1
VI + 0.3 V
- F
Table 7. Thermal characteristics
Symbol Parameter
Conditions
Rth(j-a) thermal resistance from junction to ambient
Typ
[1][2] 250
Unit
K/W
[1] The overall Rth(j-a) can vary depending on the board layout. To minimize the effective Rth(j-a), all pins must
have a solid connection to large Cu layer areas for example to the power and ground layer. In multilayer
PCB applications, the second layer should be used to create a large heat spreader area directly below the
LDO. If this layer is either ground or power, it should be connected with several vias to the top layer
connecting to the device ground or supply. Avoid the use of solder-stop varnish under the chip.
[2] Use the measurement data given for a rough estimation of the Rth(j-a) in your application. The actual Rth(j-a)
value can vary in applications using different layer stacks and layouts.
LD6835_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 20 September 2013
© NXP B.V. 2013. All rights reserved.
5 of 23
5 Page 
NXP Semiconductors
LD6835 series
Low-dropout regulator, high PSRR, 300 mA
9.6 Load regulation
Load regulation is the capability of the circuit to maintain the nominal output voltage while
varying the output load current.
---------V---O------ 100
Load regulation % mA = -V---O------n---o--m-------------------
IO
(2)
92
9
DDD
,2
$
92
9
DDD
,2
$
92
92
,2 ,2
W PV
VO(nom) = 1.2 V; IO = 1 mA to 300 mA; tr = tf = 2 s;
CL(ext) = 1 F; Cext(IN) = 1 F
Fig 14. Load regulation for LD6835K/12x
W PV
VO(nom) = 3.3 V; IO = 1 mA to 300 mA; tr = tf = 2 s;
CL(ext) = 1 F; Cext(IN) = 1 F
Fig 15. Load regulation for LD6835K/33x
LD6835_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 20 September 2013
© NXP B.V. 2013. All rights reserved.
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