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PDF QD15AL0202 Data sheet ( Hoja de datos )
| Número de pieza | QD15AL0202 | |
| Descripción | TFT LCD Module | |
| Fabricantes | AUO | |
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Hay una vista previa y un enlace de descarga de QD15AL0202 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
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Preliminary
Specification
AU Optronics Corp.
SPECIFICATION
QD15AL0202 Page 1 /25
Doc No. QD15AL0202-00
Doc. REV.: 01
Issue Date: 2006/8/28
With RoHS
compliant
Specification for TFT LCD Module
Model No.
QD15AL0202 Rev.:01
( B154SW01 V5 )
□ Approval By
AU Optronics Corp.
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4. Input Terminals
QD15AL0202 Page 5 /25
4-1. Signal Interface Connector
CN1 (2 channel, LVDS signals – NSC/Ti standard and +3.3V DC power supply)
Using connector: FI-XB30Sx-HFxx/FI-X30Sx-HFxx/equivalent (JAE)
Interface Cable Pin Assignments
PIN NO
SYMBOL
FUNCTION
1 VSS
Ground
2 VDD
Power Supply, 3.3 V (typical)
3 VDD
Power Supply, 3.3 V (typical)
4
V EEDID
DDC 3.3V power
5 NC
Reserved for supplier test point
6
Clk EEDID
DDC Clock
7 DATA EEDID DDC Data
8 Rin0- - LVDS differential data input (R0-R5, G0) (odd pixels)
9 Rin0+ + LVDS differential data input (R0-R5, G0) (odd pixels)
10 VSS
Ground
11 Rin1-
- LVDS differential data input (G1-G5, B0-B1) (odd pixels)
12 Rin1+
+ LVDS differential data input (G1-G5, B0-B1) (odd pixels)
13 VSS
Ground
14 Rin2-
- LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
15 Rin2+
+ LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
16 VSS
Ground
17 ClkIN-
- LVDS differential clock input (odd pixels)
18 ClkIN+ + LVDS differential clock input (odd pixels)
19 VSS
Ground
20 Even_Rin0- - LVDS differential data input (R0-R5, G0) (even pixels)
21 Even_Rin0+ + LVDS differential data input (R0-R5, G0) (even pixels)
22 VSS
Ground
23 Even_Rin1- - LVDS differential data input (G1-G5, B0-B1) (even pixels)
24 Even_Rin1+ + LVDS differential data input (G1-G5, B0-B1) (even pixels)
25 VSS
Ground
26 Even_Rin2- - LVDS differential data input (B2-B5, HS, VS, DE) (even pixels)
27 Even_Rin2+ + LVDS differential data input (B2-B5, HS, VS, DE) (even pixels)
28 VSS
Ground
29 Even _Clk in- - LVDS differential clock input (even pixels), 2.1V
30 Even _Clk in+ + LVDS differential clock input (even pixels), 2.1V
[Note 1] Relation between LVDS signals and actual data shows below section (4-2).
[Note 2] The shielding case is connected with signal GND.
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7. Timing characteristics of LCD module input signals
7-1. Timing characteristics
(This is specified at digital outputs of LVDS driver.)
Data
ENAB
Sync
QD15AL0202 Page 11/25
Vertical
Item symbol
Vsync cycle (TVA)
Blanking period(TVB)
Sync pulse width (TVC)
Back porch (TVD)
Sync pulse width + Back
porch (TVC+TVD)
Active display area (TVE)
Front porch (TVF)
Min.
1054
4
1
2
3
1050
1
Typ.
16.667
1080
30
6
21
27
1050
3
Max.
1099
49
40
0
40
1050
9
Unit Remark
ms Negative
line
line
line
line
line
line
line
( Horizontal )
Item symbol
Min.
Typ.
Max. Unit Remark
Hsync cycle (THA)
Blanking period (THB)
Sync pulse width (THC)
Back porch (THD)
Sync pulse width + Back
porch (THC +THD)
Active display area (THE)
Front porch (THF)
870
30
6
6
12
840
18
15.3
920
80
16
40
56
840
24
s Negative
980 clock
140 clock
110 clock
10 clock
120 clock
840 clock
20 clock
Clock
Item
Min.
Typ.
Max. Unit Remark
Frequency
55.0
59.61
64.62 MHz Note1/2
Note1 In case of lower frequency, the deterioration of display quality, flicker etc., may
be occurred.
Note2 Two pixel-data are sampled at a same time.
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