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PDF T-55708D121J-LW-A-AAN Data sheet ( Hoja de datos )
| Número de pieza | T-55708D121J-LW-A-AAN | |
| Descripción | SVGA | |
| Fabricantes | OPTREX | |
| Logotipo |  |
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TENTATIVE
All information in this technical data sheet is tentative
and subject to change without notice.
Preliminary
12.1” SVGA
TECHNICAL SPECIFICATION
T-55708D121J-LW-A-AAN
OPTREX CORPORATION
Date: Aug.8,’11
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3. ABSOLUTE MAXIMUM RATINGS
ITEM
SYMBOL
MIN.
MAX.
UNIT
Power Supply Voltage for LCD
VCC
(0)
(4.0)
V
Logic Input Voltage
VI
(−0.3) (VCC+0.3)
V
Backlight Power Supply Input Voltage
VL
(−0.3)
(14.0)
V
Backlight ON-OFF
BLEN
(−0.3)
(14.0)
V
Light Dimming Control (PWM) Input Voltage V PDIM
(−0.3)
(14.0)
V
Operation Temperature (Panel)
Note 1,2)
Top(Panel)
−30
80 °C
Operation Temperature (Ambient) Note 2)
Top(Ambient)
−30
80 °C
Storage Temperature
Note 2) Tstg −30 80 °C
[Note]
1) Measured at the center of active area and at the center of panel back surface
2) Top,Tstg ≤ 40°C : 90%RH max. without condensation
Top,Tstg > 40°C : Absolute humidity shall be less than the value of 90%RH at 40°C without
condensation.
4. ELECTRICAL CHARACTERISTICS
(1)TFT-LCD
ITEM
SYMBOL MIN.
Power Supply Voltages for LCD
VCC
(3.0)
Power Supply Currents for LCD ICC
--
Permissive Input Ripple Voltage VRP
--
Logic Input Voltage
High
Low
VIH
VIL
(0.8×VCC)
0
*1) Power and signals sequence:
t1 ≤ 10 ms
0 < t2 ≤ 50 ms
0 < t3 ≤ 50 ms
200 ms ≤ t4
200 ms ≤ t5
0 ≤ t6
0.9VCC
LCD Power Supply
Logic Signal
0.1VCC
VCC
data
Ambient temperature: Ta = 25°C
TYP.
MAX. UNIT Remarks
(3.3)
(3.6)
V
*1)
TBD
TBD
mA
*2)
-- (100) mVp-p VCC = +3.3V
--
(VCC)
V MODE, SC
-- (0.2×VCC) V MODE, SC
0.9VCC
0.1VCC 0.1VCC
t1 t2
t3 t4
Backlight Power Supply
t5 t6
data: RGB DATA, DCLK, DENA, MODE, SC
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6. INTERFACE TIMING
LVDS transmitter input signal
(1) Timing Specifications
ITEM
SYMBOL MIN
TYP
MAX
UNIT
DCLK
DENA
Frequency
Period
Active Time
Blanking Time
Horizontal
Frequency
Period
Active Time
Vertical
Blanking Time
Frequency
Period
fCLK
tCLK
tHA
tHB
fH
tH
tVA
tVB
fV
tV
(35)
(23.8)
(800)
(30)
(35.2)
(25.5)
(600)
(3)
(55)
(15.6)
(40)
(25)
(800)
(256)
(37.9)
(26.4)
(600)
(28)
(60)
(16.7)
(42)
(28.6)
(800)
--
(39.2)
(28.4)
(600)
--
(64.2)
(18.2)
MHz
ns
tCLK
tCLK
kHz
μs
tH
tH
Hz
ms
[Note]
1) DENA (Data Enable) should always be positive polarity as shown in the timing specification.
2) DCLK should appear during all invalid period.
3) LVDS timing follows the timing specifications of LVDS receiver IC: THC63LVDF84B(Thine).
4) In case of blanking time fluctuation, please satisfy following condition.
tVBn > tVBn-1 − 3(tH)
OPTREX Confidential
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T-55708D121J-LW-A-AAN
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
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