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PDF NL128102AC29-17 Data sheet ( Hoja de datos )
| Número de pieza | NL128102AC29-17 | |
| Descripción | TFT COLOR LCD MODULE | |
| Fabricantes | NLT | |
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TFT COLOR LCD MODULE
NL128102AC29-17
48cm (19.0 Type)
SXGA
LVDS interface (2port)
PRELIMINARY DATA SHEET
DOD-PP-1517 (2nd edition)
This PRELIMINARY DATA SHEET is updated
document from DOD-PP-1453(1)
All information is subject to change without notice.
Please confirm the sales representative before starting
to design your system.
Document Number: DOD-PP-1517 (2nd edition)
Published date: November 2012 CP(N)
1
© NLT Technologies, Ltd.
2012 All rights reserved.
1 page  
2. GENERAL SPECIFICATIONS
NL128102AC29-17
Display area
Diagonal size of display
Drive system
376.32 (H) × 301.056 (V) mm
48cm (19.0 inches)
a-Si TFT active matrix
Display color
16,777,216 colors
Pixel
Pixel arrangement
Dot pitch
Pixel pitch
Module size
Weight
Contrast ratio
Viewing angle
Designed viewing direction
Polarizer surface
Polarizer pencil-hardness
Color gamut
Response time
Luminance
1,280 (H) × 1,024 (V) pixels
RGB (Red dot, Green dot, Blue dot) vertical stripe
0.098 (H) × 0.294 (V) mm
0.294 (H) × 0.294 (V) mm
396.0 (W) (typ.) × 324.0 (H) (typ.) × 22.0 (D) (max.) mm
TBD g (typ.)
(1000):1 (typ.)
At the contrast ratio ≥10:1
• Horizontal: Right side 88° (typ.), Left side 88° (typ.)
• Vertical: Up side 88° (typ.), Down side 88° (typ.)
• Viewing angle with optimum grayscale (γ≒ 2.2): Normal axis
(perpendicular)
Antiglare
2H (min.) [by JIS K5600]
At LCD panel center
72% (typ.) [against NTSC color space]
Ton+Toff (10%←→ 90%)
25ms (typ.)
At the maximum luminance control
(800) cd/m2 (typ.)
2
2
2
Signal system
LVDS 2port
(Receiver: THC63LVDF84B, THine Electronics Inc. or equivalent)
[8bit digital signals for data of RGB colors, Dot clock (CLK),
Data enable (DE)]
Power supply voltage
LCD panel signal processing board: 5.0V
LED Driver board: 12.0V
Backlight
LED backlight type (with LED driver Board)
Power consumption
At BL Duty Ratio=100%, Checkered flag pattern
(45.0)W (typ.) include LED driver board
2
PRELIMINARY DATA SHEET DOD-PP-1517 (2nd edition)
5
5 Page 
4.4 POWER SUPPLY VOLTAGE SEQUENCE
4.4.1 LCD panel signal processing board
NL128102AC29-17
VDD *1
ON
4.5 V
0V 4.0 V
0.1 ms < Tr < 80 ms
OFF
4.5 V
ON
4.0 V
Toff > 200 ms
Display signals *2
TxSEL signal
0V
Note1
10 ms < t < 35 ms
VALID period
10 ms < t < 35ms
2
*1 In terms of voltage variation (voltage drop) while VDD rising edge is below 4.5 V, a
protection circuit may work, and then this product may not work.
*2 These signals should be measured at the terminal of 100 Ω resistances.
Note1: Display signals (DA0+/-, DA1+/-, DA2+/-, DA3+/-, CKA+/-, DB0+/-, DB1+/-, DB2+/-,
DB3+/-, CKB+/-) and TxSEL signal must be "0" voltage, exclude the VALID period (See
above sequence diagram). If these signals are higher than 0.3V, the internal circuit is
damaged.
If some of display and function signals of this product are cut while this product is working,
even if the signal input to it once again, it might not work normally. VDD should be cut
when the display and function signals are stopped.
Note2: VDD should be 4.5 V or more while VDD ON period.
Note3: The backlight should be turned on within the valid period of display and function signals, in
order to avoid unstable data display.
2
2
PRELIMINARY DATA SHEET DOD-PP-1517 (2nd edition)
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NL128102AC29-17.PDF ] | |
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