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PDF FDMS7602S Data sheet ( Hoja de datos )

Número de pieza FDMS7602S
Descripción Dual N-Channel PowerTrench MOSFET
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FDMS7602S Hoja de datos, Descripción, Manual

May 2014
FDMS7602S
Dual N-Channel PowerTrench® MOSFET
Q1: 30 V, 30 A, 7.5 mΩ Q2: 30 V, 30 A, 5.0 mΩ
Features
General Description
Q1: N-Channel
„ Max rDS(on) = 7.5 mΩ at VGS = 10 V, ID = 12 A
„ Max rDS(on) = 12 mΩ at VGS = 4.5 V, ID = 10 A
Q2: N-Channel
„ Max rDS(on) = 5.0 mΩ at VGS = 10 V, ID = 17 A
„ Max rDS(on) = 6.8 mΩ at VGS = 4.5 V, ID = 14 A
„ RoHS Compliant
This device includes two specialized N-Channel MOSFETs in a
dual MLP package.The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
efficiency.
Applications
„ Computing
„ Communications
„ General Purpose Point of Load
„ Notebook VCORE
S2
S2 S2
G2
S1/D2
D1
D1
D1
D1 G1
Top Bottom
Power 56
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
S2 5
S2 6
S2 7
G2 8
Symbol
VDS
VGS
ID
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
-Pulsed
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
(Note 3)
TC = 25 °C
TA = 25 °C
TA = 25 °C
TA = 25 °C
Thermal Characteristics
Q2 4 D1
3 D1
2 D1
Q1 1 G1
Q1 Q2
30 30
±20 ±20
30
121a
30
171b
40
2.21a
1.01c
60
2.51b
1.01d
-55 to +150
Units
V
V
A
W
°C
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
571a
1251c
3.5
501b
1201d
2
°C/W
Device Marking
FDMS7602S
Device
FDMS7602S
Package
Power 56
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
©2010 Fairchild Semiconductor Corporation
FDMS7602S Rev.C2
1
www.fairchildsemi.com

1 page




FDMS7602S pdf
Typical Characteristics (Q1 N-Channel)TJ = 25°C unless otherwise noted
10
ID = 12 A
8
6
4
2
VDD = 10 V
VDD = 15 V
VDD = 20 V
0
0 5 10 15 20
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
2000
1000
Ciss
Coss
100
f = 1 MHz
Crss
VGS = 0 V
10
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure 8. Capacitance vs Drain
to Source Voltage
60
VGS = 10 V
40
VGS = 4.5 V
20 Limited by Package
RθJC = 3.5 oC/W
0
25 50 75 100 125
TC, CASE TEMPERATURE (oC)
Figure 9. Maximum Continuous Drain
Current vs Case Temperature
150
100
100us
10
1 ms
1
THIS AREA IS
LIMITED BY rDS(on)
10 ms
100 ms
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 125 oC/W
TA = 25 oC
0.01
0.01 0.1
1
1s
10s
DC
10 100 200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 10. Forward Bias Safe
Operating Area
1000
100
SINGLE PULSE
RθJA = 125 oC/W
TA = 25 oC
10
1
0.5
10-4
10-3
10-2
10-1
1
t, PULSE WIDTH (s)
10
Figure 11. Single Pulse Maximum Power Dissipation
©2010 Fairchild Semiconductor Corporation
FDMS7602S Rev.C2
100 1000
www.fairchildsemi.com

5 Page





FDMS7602S arduino
0.05 C
2X
5.00
AB
6.00
0.63(5X)
8
0.25
4.46
1.27
76
0.65
5
0.40
PIN#1 IDENT
0.10 C
0.08 C
SIDE VIEW
0.05 C
2X
2.67
0.54
0.92
6.30
0.66
C
SEATING
PLANE
0.65 (5X)
1
23
4.00
4
RECOMMENDED LAND PATTERN
(OPTION 1 - FUSED LEADS 5,6,7)
(0.34)4X
12
34
PIN#1 IDENT
(0.66)
0.63(8X)
8
4.46
1.27
76
0.65(8X)
5
0.40
0.45
8
0.10 C A B
0.05 C
76
1.27
5
BOTTOM VIEW
NOTES:
A. PACKAGE DOES NOT FULLY CONFORM TO
JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
E. DRAWING FILENAME: MKT-MLP08Prev2.
2.67
0.54
0.92
6.30
0.66
12
3
4.00
4
RECOMMENDED LAND PATTERN
(OPTION 2 - ISOLATED LEADS)

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