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PDF EN25T16 Data sheet ( Hoja de datos )

Número de pieza EN25T16
Descripción 16 Mbit Uniform Sector / Serial Flash Memory
Fabricantes EON 
Logotipo EON Logotipo



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EN25T16
EN25T16
16 Mbit Uniform Sector, Serial Flash Memory with Dual Data Mode
FEATURES
Single power supply operation
- Full voltage range: 2.7-3.6 volt
16 Mbit Serial Flash
- 16 M-bit/2048 K-byte/8192 pages
- 256 bytes per programmable page
High performance
- 100MHz clock rate
- dual data mode
Low power consumption
- 5 mA typical active current
- 1 µA typical power down current
Uniform Sector Architecture:
- 512 sectors of 4-Kbyte
- 32 blocks of 64-Kbyte
- Any sector or block can be
erased individually
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
High performance program/erase speed
- Page program time: 1.5ms typical
- Sector erase time: 150ms typical
- Block erase time 800ms typical
- Chip erase time: 18 Seconds typical
Lockable 512 byte OTP security sector
Minimum 100K endurance cycle
Package Options
- 8 pins SOP 200mil body width
- 8 pins PDIP
- 8 contact VDFN
- 16 pin SOP 300mil body width
- All Pb-free packages are RoHS compliant
Commercial and industrial temperature
Range
GENERAL DESCRIPTION
The EN25T16 is a 16M-bit (2048K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25T16 is designed to allow either single Sector at a time or full chip erase operation. The
EN25T16 can be configured to protect part of the memory as the software protected mode. The device
can sustain a minimum of 100K program/erase cycles on each sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2008/01/08

1 page




EN25T16 pdf
EN25T16
MEMORY ORGANIZATION
The memory is organized as:
2,097,152 bytes
Uniform Sector Architecture
32 blocks of 64-Kbyte
512 sectors of 4-Kbyte
8192 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
Table 2. Uniform Block Sector Architecture
Block
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Sector
511
496
495
480
479
464
463
448
447
432
431
416
415
400
399
384
383
368
367
352
351
336
335
320
319
304
303
288
287
272
271
256
1FF000
1F0000
1EF000
1E0000
1DF000
1D0000
1CF000
1C0000
1BF000
1B0000
1AF000
200000
19F000
190000
18F000
180000
17F000
170000
16F000
160000
15F000
150000
14F000
140000
13F000
130000
12F000
120000
11F000
110000
10F000
100000
Address range
1FFFFF
1F0FFF
1EFFFF
1E0FFF
1DFFFF
1D0FFF
1CFFFF
1C0FFF
1BFFFF
1B0FFF
1AFFFF
200FFF
19FFFF
190FFF
18FFFF
180FFF
17FFFF
170FFF
16FFFF
160FFF
15FFFF
150FFF
14FFFF
140FFF
13FFFF
130FFF
12FFFF
120FFF
11FFFF
110FFF
10FFFF
100FFF
This Data Sheet may be revised by subsequent versions
5
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2008/01/08

5 Page





EN25T16 arduino
EN25T16
Manufacturer/
Device ID
Read Identification
Enter EXT mode
Enter OTP mode
90h
9Fh
0Ah
3Ah
dummy
(M7-M0)
dummy
(ID15-ID8)
00h(5) (M7-M0)
(ID7-ID0)
(ID7-ID0)
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from
the device on the DO pin.
2. The Status Register contents will repeat continuously until CS# terminate the instruction.
3. All sectors may use any address within the sector.
4. The Device ID will repeat continuously until CS# terminate the instruction.
5. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminate the instruction.
00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID.
Table 5. Manufacturer and Device Identification
OP Code (M7-M0)
(ID15-ID0)
(ID7-ID0)
ABh 14h
90h 1Ch
14h
9Fh 1Ch
5115h
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 5) sets the Write Enable Latch (WEL) bit. The Write Enable
Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip
Erase (CE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the instruction
code, and then driving Chip Select (CS#) High.
Figure 5. Write Enable Instruction Sequence Diagram
Write Disable (WRDI) (04h)
The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0 or exit from EXT / OTP mode to normal mode. The Write Disable instruction is entered by driving Chip
Select (CS#) low, shifting the instruction code “04h” into the DI pin and then driving Chip Select (CS#)
high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status
Register, Page Program, Sector Erase, Block Erase (BE) and Chip Erase instructions.
This Data Sheet may be revised by subsequent versions 11
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2008/01/08

11 Page







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