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Número de pieza | TC58NVG4D2FTA00 | |
Descripción | 16 GBIT (4G x 8 BIT) CMOS NAND E2PROM | |
Fabricantes | Toshiba | |
Logotipo | ||
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No Preview Available ! TOSHIBA CONFIDENTIAL TC58NVG4D2FTA00
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
16 GBIT (4G × 8 BIT) CMOS NAND E2PROM (Multi-Level-Cell)
DESCRIPTION
The TC58NVG4D2 is a single 3.3 V 16 Gbit (18,367,119,360 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as (8192 + 448) bytes × 128 pages × 2076 blocks.
The device has two 8640-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 8640-byte increments. The Erase operation is implemented in a single block
unit (1 Mbytes + 56 Kbytes: 8640 bytes × 128 pages).
The TC58NVG4D2 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
Memory cell array
Register
Page size
Block size
TC58NVG4D2F
8640 × 259.5K × 8
8640 × 8
8640 bytes
(1M + 56 K) bytes
• Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Mullti Page Read
• Mode control
Serial input/output
Command control
• Number of valid blocks
Min 1968 blocks
Max 2076 blocks
• Power supply
VCC = 2.7 V to 3.6 V
• Access time
Cell array to register 250 µs max
Serial Read Cycle
25 ns min
• Program/Erase time
Auto Page Program
Auto Block Erase
1600 µs/page typ.
4 ms/block typ.
• Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
TBD ( 50 mA max.)
TBD ( 50 mA max.)
TBD ( 50 mA max.)
100 µA max
• Package
(Weight: TBD g typ.)
• FOR RELIABILITY GUIDANCE, PLEASE REFER TO THE APPLICATION NOTES AND COMMENTS (17).
24 bit ECC for each 1024 bytes is required.
1 Rev 1.2 2009-09-14C
1 page TOSHIBA CONFIDENTIAL TC58NVG4D2FTA00
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70 , VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tCLS
CLE Setup Time
0 ⎯ ns
tCLS2
CLE Setup Time
30 ⎯ ns
tCLH
CLE Hold Time
5 ⎯ ns
tCS CE Setup Time
8 ⎯ ns
tCS2
CE Setup Time
20 ⎯ ns
tCH CE Hold Time
5 ⎯ ns
tWP Write Pulse Width
12 ⎯ ns
tALS
ALE Setup Time
0 ⎯ ns
tALH
ALE Hold Time
5 ⎯ ns
tDS Data Setup Time
10 ⎯ ns
tDH Data Hold Time
5 ⎯ ns
tWC Write Cycle Time
25 ⎯ ns
tWH WE High Hold Time
10 ⎯ ns
tWHW *
WE High Hold Time from final address to first data
120 ⎯ ns
tWW
WP High to WE Low
100 ⎯ ns
tRR Ready to RE Falling Edge
20 ⎯ ns
tRW Ready to WE Falling Edge
20 ⎯ ns
tRP Read Pulse Width
12 ⎯ ns
tRC Read Cycle Time
25 ⎯ ns
tREA
RE Access Time
⎯ 20 ns
tCR CE Low to RE Low
10 ⎯ ns
tCLR
CLE Low to RE Low
10 ⎯ ns
tAR ALE Low to RE Low
10 ⎯ ns
tRHOH
Data Output Hold Time from RE High
25 ⎯ ns
tRLOH
Data Output Hold Time from RE Low
5 ⎯ ns
tRHZ
RE High to Output High Impedance
⎯ 60 ns
tCHZ
CE High to Output High Impedance
⎯ 30 ns
tCLHZ
CLE High to Output High Impedance
⎯ 30 ns
tREH
RE High Hold Time
10 ⎯ ns
tIR Output-High-impedance-to- RE Falling Edge
0 ⎯ ns
tRHW
RE High to WE Low
30 ⎯ ns
tWHC
WE High to CE Low
30 ⎯ ns
tWHR1
WE High to RE Low (Status Read)
180 ⎯ ns
tWHR2
WE High to RE Low (Column Address Change in Read)
300 ⎯ ns
tR Memory Cell Array to Starting Address
⎯ 250 µs
tDCBSYR1 Data Cache Busy in Read Cache (following 31h and 3Fh)
⎯ 250 µs
tDCBSYR2 Data Cache Busy in Page Copy (following 3Ah)
⎯ 255 µs
tWB WE High to Busy
⎯ 100 ns
tRST
Device Reset Time (Ready/Read/Program/Erase)
⎯
10/10/30/500
µs
* tWHW is the time from the WE rising edge of final address cycle to the WE falling edge of first data cycle.
5 Rev 1.2 2009-09-14C
5 Page Read Cycle with Data Cache Timing Diagram (1/2)
TOSHIBA CONFIDENTIAL TC58NVG4D2FTA00
CLE
CE
tCLS tCLH
tCS tCH
tWC
WE
tALH tALS
tCLS tCLH
tCS tCH
tCLR
tCLS tCLH
tCS tCH
tALH tALS
tRW tCR
tCLR
tCLS tCLH
tCS tCH
tCR
ALE
RE
I/O
RY / BY
tDS tDH
00h
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
CA0
to 7
CA8
to 13
Column address
N*
PA0 PA8 PA16
to 7 to 15 to 18
Page address
M
tR
tWB
tDS tDH
30h
tDCBSYR1
tRC
tWB
tDS tDH
31h
tRR tREA
DOUT DOUT
01
DOUT
Page address M
Col. Add. 0
tDCBSYR1
tWB
tDS tDH
31h
tRR tREA
DOUT
0
Page address
M+1
Col. Add. 0
* The column address will be reset to 0 by the 31h command input.
1
Continues to 1 of next page
11 Rev 1.2 2009-09-14C
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet TC58NVG4D2FTA00.PDF ] |
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