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PDF LC550EUH-RDA2 Data sheet ( Hoja de datos )

Número de pieza LC550EUH-RDA2
Descripción WUXGA TFT LCD
Fabricantes RAKEN 
Logotipo RAKEN Logotipo



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Product Specification
SPECIFICATION
FOR
APPROVAL
LC550EUH
( ̻ ) Preliminary Specification
( ) Final Specification
Title
55.0” WUXGA TFT LCD
BUYER
MODEL
LGE
SUPPLIER
RAKEN Co., Ltd.
*MODEL
LC550EUH
SUFFIX
RDA2
*When you obtain standard approval,
please use the above model name without suffix
APPROVED BY
/
SIGNATURE
DATE
APPROVED BY
Charlie.Ko/ Team Leader
SIGNATURE
DATE
REVIEWED BY
/ Power.Zheng/ Engineer
/
Please return 1 copy for your confirmation with
your signature and comments.
Ver. 1.0
PREPARED BY
Suxi.Jiang/ Engineer
TV R&D LCM Qualification Dept.
RAKEN Co., Ltd.
0 /34
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LC550EUH-RDA2 pdf
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Product Specification
LC550EUH
1. General Description
The LC550EUH is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED)
backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive type display operating in the normally black mode. It has a 54.64 inch diagonally measured
active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 16.7M(true) colors.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.
Power (VCC, VDD, HVDD, VGH, VGL)
Source Control Signal
Gate Control Signal
Gamma Reference Voltage
CN1
(60pin)
mini-LVDS (RGB) for Left drive
Power (VCC, VDD, HVDD, VGH, VGL)
Source Control Signal
Gate Control Signal
Gamma Reference Voltage
CN2
(60pin)
mini-LVDS (RGB) for Right drive
S1
G1
Source Driver Circuit
S1920
TFT - LCD Panel
(1920 Ý RGB Ý 1080 pixels)
[Gate In Panel]
G1080
LED Anode
LED Cathode
General Features
Active Screen Size
Outline Dimension
Pixel Pitch
Pixel Format
Color Depth
Drive IC Data Interface
Luminance, White
Viewing Angle (CR>10)
Power Consumption
Weight
Display Operating Mode
Surface Treatment
Ver. 1.0
CN1(12pin)
CN2 (13pin)
H : 8Block
V : 2Block
Local Dimming : 16 Block
54.64 inches(1387.8mm) diagonal
1255.6(H) x 726.4.0 (V) x10.8 (D) (Typ.)
0.630 mm x 0.630 mm
1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
8-bit, 16.7 M colors (1.06B colors @ 10 bit (D) System Output )
Source D-IC : 8-bit mini-LVDS, and control signals TTL
Gate D-IC : Line on Glass (LOG) Through Source D-IC
400 cd/m2 (Center 1point ,Typ.)
Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))
Total 126.1W [Logic= 6.1W, B/L=120W (ExtVbr_B=100% )]
14.5Kg (Typ.)
Transmissive mode, Normally black
Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 10%)
4 /34
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LC550EUH-RDA2 arduino
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Product Specification
LC550EUH
-LCD Connector (CN2): TF06L-60S-0.5SH(Manufactured by HRS)
Table 3-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION
No Symbol
Description
͑ No Symbol
Description
͢
͸;Ͳ͑͢ ͸Ͳ;;Ͳ͑·΀ͽ΅Ͳ͸Ͷ͙͑͑͑͑͑͢΀ΦΥΡΦΥ͑ΗΣΠΞ͑ͽʹ͵͚͑͑ 31
RLV1 + Right Mini LVDS Receiver Signal(1+)
ͣ ͸;Ͳ͑ͤ ͸Ͳ;;Ͳ͑·΀ͽ΅Ͳ͸Ͷ͑ͤ
͑ 32
RLV0 - Right Mini LVDS Receiver Signal(0-)
ͤ ͸;Ͳ͑ͥ ͸Ͳ;;Ͳ͑·΀ͽ΅Ͳ͸Ͷ͑ͥ
͑ 33
RLV0 + Right Mini LVDS Receiver Signal(0+)
ͥ ͸;Ͳ͑ͦ ͸Ͳ;;Ͳ͑·΀ͽ΅Ͳ͸Ͷ͑ͦ
͑ 34
GND
Ground
ͦ ͸;Ͳ͑ͨ ͸Ͳ;;Ͳ͑·΀ͽ΅Ͳ͸Ͷ͑ͨ
͑ 35
VCC
Logic Power Supply Voltage
ͧ ͸;Ͳ͑ͪ ͸Ͳ;;Ͳ͑·΀ͽ΅Ͳ͸Ͷ͙͑ͪ͑͑͑͑΀ΦΥΡΦΥ͑ΗΣΠΞ͑ͽʹ͵͚͑͑ 36
VCC
Logic Power Supply Voltage
ͨ ͸;Ͳ͑͢͡ ͸Ͳ;;Ͳ͑·΀ͽ΅Ͳ͸Ͷ͙͑͑͑͢͡΀ΦΥΡΦΥ͑ΗΣΠΞ͑ͽʹ͵͚͑͑ 37
GND
Ground
ͩ ͸;Ͳ͑ͣ͢ ͸Ͳ;;Ͳ͑·΀ͽ΅Ͳ͸Ͷ͑ͣ͢
͑ 38
H_VDD Half Driver Power Supply Voltage
ͪ ͸;Ͳ͑ͥ͢ ͸Ͳ;;Ͳ͑·΀ͽ΅Ͳ͸Ͷ͑ͥ͢
͑ 39
H_VDD Half Driver Power Supply Voltage
͢͡ ͸;Ͳ͑ͦ͢ ͸Ͳ;;Ͳ͑·΀ͽ΅Ͳ͸Ͷ͑ͦ͢
͑ 40
VDD
Driver Power Supply Voltage
͢͢ ͸;Ͳ͑ͧ͢ ͸Ͳ;;Ͳ͑·΀ͽ΅Ͳ͸Ͷ͑ͧ͢
͑ 41
VDD
Driver Power Supply Voltage
ͣ͢ ͸;Ͳ͑ͩ͢ ͸Ͳ;;Ͳ͑·΀ͽ΅Ͳ͸Ͷ͙͑ͩ͑͑͢΀ΦΥΡΦΥ͑ΗΣΠΞ͑ͽʹ͵͚͑͑ 42
GND
Ground
ͤ͢
GND
Ground
͑ 43
GND
Ground
ͥ͢ OPT_N “H” Normal Display
͑ 44 VCOM_R VCOM Right Input
ͦ͢ H_CONV "H“ H 2dot Inversion/ "L" H 1dot Inversion ͑ 45 VCOM_R_FB VCOM Right Feed-Back Output
ͧ͢
GSP
GATE Start Pulse
͑ 46
GND
Ground
ͨ͢
POL
Polarity Control Signal
͑ 47
VGL
GATE Low Voltage
ͩ͢
SOE
Source Output Enable SIGNAL
͑ 48
VGL
GATE Low Voltage
ͪ͢
GND
Ground
͑ 49
GND
Ground
ͣ͡ RLV5 - Right Mini LVDS Receiver Signal(5-)
͑ 50
GND
Ground
ͣ͢ RLV5 + Right Mini LVDS Receiver Signal(5+)
͑ 51
VGH
GATE High Voltage
ͣͣ RLV4 - Right Mini LVDS Receiver Signal(4-)
͑ 52
VGH
GATE High Voltage
ͣͤ RLV4 + Right Mini LVDS Receiver Signal(4+)
͑ 53
GND
Ground
ͣͥ RLV3 - Right Mini LVDS Receiver Signal(3-)
͑ 54
GOE
GATE Output Enable
ͣͦ RLV3 + Right Mini LVDS Receiver Signal(3+)
͑ 55
GSC
GATE Shift Clock
ͣͧ LCLK - Right Mini LVDS Receiver Clock Signal(-) ͑ 56
GND
Ground
ͣͨ LCLK + Right Mini LVDS Receiver Clock Signal(+) ͑ 57 OPT_P “L” Normal Display
ͣͩ RLV2 - Right Mini LVDS Receiver Signal(2-)
͑ 58
GND
Ground
ͣͪ RLV2 + Right Mini LVDS Receiver Signal(2+)
͑ 59
NC No Connection
ͤ͡ RLV1 - Right Mini LVDS Receiver Signal(1-)
͑ 60 ͽ΅͵ΐ΀Ά΅ ͽ΅͵͑΀Ά΅΁Ά΅
Note : 1. Please refer to application note for details
(Half VDD & Gamma Voltage & H_CONV setting)
2. These 'input signal' (OPT_N,H_CONV) should be connected
Source Right PCB
Ver. 1.0
CN 2
#1 #60
CN 1
#1 #60
Source Left PCB
10 /34
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