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Número de pieza | LC470EUG-RDV2 | |
Descripción | WUXGA TFT LCD | |
Fabricantes | RAKEN | |
Logotipo | ||
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Product Specification
SPECIFICATION
FOR
APPROVAL
LC470EUG
( ) Preliminary Specification
( ̻ ) Final Specification
Title
47.0” WUXGA TFT LCD
BUYER
MODEL
LGE
SUPPLIER
RAKEN Co., Ltd.
*MODEL
LC470EUG
SUFFIX
RDV2
*When you obtain standard approval,
please use the above model name without suffix
APPROVED BY
/
SIGNATURE
DATE
APPROVED BY
Charlie.Ko/ Team Leader
SIGNATURE
DATE
REVIEWED BY
/ Power.Zheng/ Engineer
/
Please return 1 copy for your confirmation with
your signature and comments.
Ver. 1.0
PREPARED BY
Suxi.Jiang/ Engineer
TV R&D LCM Qualification Dept.
RAKEN Co., Ltd.
0 /35
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Product Specification
LC470EUG
1. General Description
The LC470EUG is a Color Active Matrix Liquid Crystal Display with an integral the Source PCB and Gate
implanted on Panel (GIP). The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive type display operating in the normally black mode. It has a 46.96 inch diagonally measured
active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 16.7M(true) colors.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.
Power (VCC,VDD,HVDD,VGH,VGL)
Source Control Signal
Gate Control Signal
Gamma Reference Voltage
CN1
(60pin)
mini-LVDS (RGB) for Left drive
Power (VCC,VDD,HVDD,VGH,VGL)
Source Control Signal
Gate Control Signal
Gamma Reference Voltage
CN2
(60pin)
mini-LVDS (RGB) for Right drive
S1
G1
Source Driver Circuit
S1920
TFT - LCD Panel
(1920 Ý RGB Ý 1080 pixels)
[Gate In Panel]
G1080
LED Anode
LED Cathode
General Features
Active Screen Size
Outline Dimension
Pixel Pitch
Pixel Format
Color Depth
Luminance, White
Viewing Angle (CR>10)
Power Consumption
Weight
Display Operating Mode
Surface Treatment
Ver. 1.0
CN1 (12pin)
CN2 (13pin)
V : 3Block
46.96inches(1192.87mm) diagonal
1078.6(H) Ý 626.0(V) X 10.8(B)/22.9 mm(D) (Typ.)
0.5415 mm x 0.5415 mm
1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
8bit, 16,7 M colors
360 cd/m2 (Center 1point ,Typ.)
Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))
Total 100.2W [Logic= 7.1W, LED Driver=93.1W (ExtVbr_B=100% )]
12.7 Kg (Typ.)
Transmissive mode, normally black
Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 10%)
4 /35
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Product Specification
LC470EUG
-LCD Connector (CN2): TF06L-60S-0.5SH(Manufactured by HRS)
Table 3-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION
No Symbol
Description
No Symbol
Description
͢ ;Ͳ͑͢ Ͳ;;Ͳ͑·ͽ΅ͲͶ͙͑͑͑͢ΦΥΡΦΥ͑ͷΣΠΞ͑ͽʹ͵͚ 31 RLV1 + Right Mini LVDS Receiver Signal(1+)
ͣ ;Ͳ͑ͤ Ͳ;;Ͳ͑·ͽ΅ͲͶ͑ͤ
32 RLV0 - Right Mini LVDS Receiver Signal(0-)
ͤ ;Ͳ͑ͥ Ͳ;;Ͳ͑·ͽ΅ͲͶ͑ͥ
33 RLV0 + Right Mini LVDS Receiver Signal(0+)
ͥ ;Ͳ͑ͦ Ͳ;;Ͳ͑·ͽ΅ͲͶ͑ͦ
34
GND
Ground
ͦ ;Ͳ͑ͨ Ͳ;;Ͳ͑·ͽ΅ͲͶ͑ͨ
35
VCC
Logic Power Supply Voltage
ͧ
;Ͳ͑ͪ Ͳ;;Ͳ͑·ͽ΅ͲͶ͙͑ͪ͑͑ΦΥΡΦΥ͑ͷΣΠΞ͑ͽʹ͵͚
36
VCC
Logic Power Supply Voltage
ͨ ;Ͳ͑͢͡ Ͳ;;Ͳ͑·ͽ΅ͲͶ͙͑͑͢͡ΦΥΡΦΥ͑ͷΣΠΞ͑ͽʹ͵͚ 37
GND
Ground
ͩ ;Ͳ͑ͣ͢ Ͳ;;Ͳ͑·ͽ΅ͲͶ͑ͣ͢
38 H_VDD Half Driver Power Supply Voltage
ͪ ;Ͳ͑ͥ͢ Ͳ;;Ͳ͑·ͽ΅ͲͶ͑ͥ͢
39 H_VDD Half Driver Power Supply Voltage
͢͡ ;Ͳ͑ͦ͢ Ͳ;;Ͳ͑·ͽ΅ͲͶ͑ͦ͢
40
VDD
Driver Power Supply Voltage
͢͢ ;Ͳ͑ͧ͢ Ͳ;;Ͳ͑·ͽ΅ͲͶ͑ͧ͢
41
VDD
Driver Power Supply Voltage
ͣ͢ ;Ͳ͑ͩ͢ Ͳ;;Ͳ͑·ͽ΅ͲͶ͙͑ͩ͑͢ΦΥΡΦΥ͑ͷΣΠΞ͑ͽʹ͵͚ 42
GND
Ground
ͤ͢
GND
Ground
43
GND
Ground
ͥ͢ OPT_N “H” Normal Display / “L” Rotation Display
44 VCOM_R VCOM Right Input
ͦ͢ H_CONV "H“ H 2dot Inversion/ "L" H 1dot Inversion
45 VCOM_R_FB VCOM Right Feed-Back Output
ͧ͢
GSP
GATE Start Pulse
46 GIP_Reset GIP Reset
ͨ͢
POL
Polarity Control Signal
47 VST VERTICAL START PULSE
ͩ͢
SOE
Source Output Enable SIGNAL
48
VGL
GATE Low Voltage
ͪ͢
GND
Ground
49 VGH_EVEN GIP Panel VDD for Even GATE TFT
ͣ͡ Ϳʹ ͿΠ͑ʹΠΟΟΖΔΥΚΠΟ
50 VGH_ODD GIP Panel VDD for Odd GATE TFT
ͣ͢ Ϳʹ ͿΠ͑ʹΠΟΟΖΔΥΚΠΟ
51 VGI_P GIP Bi-Scan (Normal =VGH Rotate = VGL)
ͣͣ Ϳʹ ͿΠ͑ʹΠΟΟΖΔΥΚΠΟ
52 VGI_N GIP Bi-Scan (Normal =VGL Rotate = VGH)
ͣͤ Ϳʹ ͿΠ͑ʹΠΟΟΖΔΥΚΠΟ
53 GCLK6 GIP GATE Clock 6
ͣͥ Ϳʹ ͿΠ͑ʹΠΟΟΖΔΥΚΠΟ
54 GCLK5 GIP GATE Clock 5
ͣͦ Ϳʹ ͿΠ͑ʹΠΟΟΖΔΥΚΠΟ
55 GCLK4 GIP GATE Clock 4
ͣͧ RCLK - Right Mini LVDS Receiver Clock Signal(-)
56 GCLK3 GIP GATE Clock 3
ͣͨ RCLK + Right Mini LVDS Receiver Clock Signal(+) 57 GCLK2 GIP GATE Clock 2
ͣͩ RLV2 - Right Mini LVDS Receiver Signal(2-)
58 GCLK1 GIP GATE Clock 1
ͣͪ RLV2 + Right Mini LVDS Receiver Signal(2+)
59 Ϳʹ ͿΠ͑ʹΠΟΟΖΔΥΚΠΟ
ͤ͡ RLV1 - Right Mini LVDS Receiver Signal(1-)
60 ͽ΅͵ΐΆ΅ ͽ΅͵͑Ά΅Ά΅
Note :
1. Please refer to application note for details
(GIP & Gamma Voltage setting)
Source Right PCB
Ver. 1.0
CN 2
#1 #60
CN 1
#1 #60
Source Left PCB
10 /35
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11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet LC470EUG-RDV2.PDF ] |
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