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PDF EP9142 Data sheet ( Hoja de datos )

Número de pieza EP9142
Descripción HDMI 1.4 Splitter
Fabricantes Yi Shun Electronics 
Logotipo Yi Shun Electronics Logotipo



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HDMI 1.4 Splitter
EP9142
User Guide — EP9142_UG V0.1
User Guide
V0.1
Revised: Apr. 26, 2011
Original Release Date: May. 12, 2010
惠东益顺电子厂
Explore
Explore reserves the right to make changes without further notice to any products herein to improve reliability, function or design.
Explore does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it
convey any license under its patent rights nor the rights of others. Explore products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for
any other application in which the failure of the Explore product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Explore products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Explore and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses,
and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended
or unauthorized use, even if such claim alleges that Explore was negligent regarding the design or manufacture of the part.
Explore Confidential Proprietry
NON-DISCLOSURE AGREEMENT REQUIRED
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EP9142 pdf
Section 2 Overview
2.1 Block Diagram
Figure 2-1 Block Diagram
User Guide — EP9142_UG V0.1
MCU_SDA
MCU_SCL
EXT_RSTb
EXT_SWING
DDC_SDA
DDC_SCL
IIC Slave
Registers
&
Logics
IIC Slave
DVI/HDMI
Receiver
HDCP Keys
惠东益顺电子厂
DVI/HDMI
Transmitter
HDCP Keys
HDCP Keys
DVI/HDMI
Transmitter
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NON-DISCLOSURE AGREEMENT REQUIRED
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EP9142 arduino
Section 3 Detail Functional Descriptions
User Guide — EP9142_UG V0.1
3.1 General
The chip provides an IIC (SCL3/SDA3) serial bus interface to communicate with the host. The IIC address
for this slave IIC interface is “0111_0_A1_0_x” (where x=1 for read and x=0 for write). A1 is
programmable by pin.
3.2 IIC Interface
The IIC bus interface uses a Serial Data line (SDA at pin SDA3) and a Serial Clock Line (SCL at pin SCL3)
for data transfer. The chip acts as a slave for receiving and transmitting data over the serial interface. All
devices connected to the IIC bus must have open drain or open collector outputs. Logic AND function is
exercised on both lines with external pull-up resistors, the value of these resistors is system dependent.
When the serial interface is not active, the logic levels on SCL and SDA are pulled HIGH by external
pull-up resistors.
Data received or transmitted on the SDA line must be stable at the positive edge of SCL. If the SDA changes
state while SCL is HIGH, the IIC interface interprets that action as a START or STOP sequence. Data on
SDA must change only when SCL is LOW.
The standard IIC traffic protocol is illustrated in the following Figure:
惠东益顺电子厂Figure 3-1 IIC Bus Transmission Protocol
MSB LSB MSB LSB
SCL 1 2 3 4 5 6 7 8 9
1 2 34 5 6 78 9
SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX D7 D6 D5 D4 D3 D2 D1 D0
Start
Signal
Calling Address
Read/ Ack
Write Bit
MSB LSB
SCL 1 2 3 4 5 6 7 8 9
Data Byte
No Stop
Ack Signal
Bit
MSB LSB
1 234 5 678 9
SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XX
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Start
Signal
Calling Address
Read/ Ack Repeated
Write Bit
Start
Signal
New Calling Address
Read/ No Stop
Write
Ack
Bit
Signal
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