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PDF RTL8192CE-GR Data sheet ( Hoja de datos )

Número de pieza RTL8192CE-GR
Descripción SINGLE-CHIP IEEE 802.11b/g/n 2T2R WLAN CONTROLLER w/PCI EXPRESS INTERFACE
Fabricantes Realtek 
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RTL8192CE-GR
SINGLE-CHIP IEEE 802.11b/g/n 2T2R WLAN
CONTROLLER w/PCI EXPRESS INTERFACE
DATASHEET
Rev. 0.1
29 October 2009
Track ID:
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com

1 page




RTL8192CE-GR pdf
RTL8192CE
Datasheet
1. General Description
The Realtek RTL8192CE is a highly integrated single-chip MIMO (Multiple In, Multiple Out) Wireless
LAN (WLAN) solution for the wireless high throughput 802.11n specification. It combines a MAC, a 2T2R
capable baseband, and RF in a single chip. The RTL8192CE provides a complete solution for a high
throughput performance wireless client.
The RTL8192CE baseband implements Multiple Input, Multiple Output (MIMO) Orthogonal Frequency
Division Multiplexing (OFDM) with 2 transmit and 2 receive paths (2T2R) and is compatible with the
IEEE 802.11n specification. Features include two spatial streams transmission, short guard interval (GI) of
400ns, spatial spreading, and transmission over 20MHz and 40MHz bandwidth. Moreover, RTL8192CE
provides one spatial stream space-time block code (STBC) to extend the range of transmission. At the
receiver, extended range and good minimum sensitivity is achieved by having receiver diversity up to 2
antennas. As the recipient, the RTL8192CE also supports explicit sounding packet feedback that helps
senders with beamforming capability. With 2 independent RF blocks, the RTL8192CE can perform fast
roaming without link interruption.
For legacy compatibility, direct sequence spread spectrum (DSSS), complementary code keying (CCK) and
OFDM baseband processing are included to support all IEEE 802.11b and 802.11g data rates. Differential
phase shift keying modulation schemes, DBPSK and DQPSK with data scrambling capability, are available
along with complementary code keying to provide the data rates of 1, 2, 5.5 and 11Mbps with long or short
preamble. The high speed FFT/IFFT paths, combined with BPSK, QPSK, 16QAM, and 64QAM
modulation of the individual subcarriers and rate compatible punctured convolutional coding with coding
rate of 1/2, 2/3, 3/4, and 5/6, provides the maximum data rate of 54Mbps and 300Mbps for IEEE 802.11g
and 802.11n MIMO OFDM respectively.
The RTL8192CE builds in an enhanced signal detector, an adaptive frequency domain equalizer, and a
soft-decision Viterbi decoder to alleviate the severe multi-path effects and mutual interference in the
reception of multiple streams. For better detection quality, receive diversity with maximal-ratio-combine
(MRC) applying up to 2 receive paths are implemented. Robust interference detection and suppression are
provided to protect against bluetooth, cordless phone, and microwave oven. Receive vector diversity for
multi-stream application is implemented for efficient utilization of MIMO channel. Efficient IQ-imbalance,
DC offset, phase noise, frequency offset and timing offset compensations are provided for the radio
frequency front-end impairments. Selectable digital transmit and receiver FIR filters are provided to meet
transmit spectrum mask requirements and to reject adjacent channel interference, respectively.
Single-Chip IEEE 802.11b/g/n 2T2R WLAN Controller
with PCI Express Interface
1
Track ID: Rev.0.1

5 Page





RTL8192CE-GR arduino
4.1. Package Identification
Green package is indicated by a ‘G’in the location marked ‘T’in Figure 2.
RTL8192CE
Datasheet
5. Pin Descriptions
The following signal type codes are used in the tables:
I: Input
O: Output
T/S: Tri-State bi-directional input/output pin
S/T/S: Sustained Tri-State
O/D: Open Drain
P: Power pin
5.1. PCI Express Transceiver Interface
Symbol
HSIN/HSIP
HSON/HSOP
REFCLK_P/R
EFCLK_N
CLKREQn
Type
I
O
I
O
WAKEn
PERSTn
O/D
I
Table 1. PCI Express Transceiver Interface
Pin No
59/60
Description
PCI Express Receive Differential Pair
55/56
PCI Express Transmit Differential Pair
57/58
PCI Express Differential Reference Clock Source: 100MHz ± 300ppm
51 Reference Clock Request Signal
This signal is used by the RTL8192CE-GR to request starting of the PCI
Express reference clock
50 Power Management Event: Open drain, active low
Used to reactivate the PCI Express slot’s main power rails and reference clocks.
52 PCI Express Reset Signal: Active low
When the PERSTB is asserted at power-on state, the RTL8192CE-GR returns
to a pre-defined reset state and is ready for initialization and configuration
after the de-assertion of the PERSTB.
5.2. EEPROM Interface
Symbol
EESK
EEDI
EEDO
EECS
Type
O
O
IO
O
Pin No
14
13
12
15
Table 2. EEPROM Interface
Description
EESK in 93C46 Programming or Auto-Load Mode
EEDI in 93C46 Programming or Auto-Load Mode
EEDO in 93C46 Programming or Auto-Load Mode
EEPROM Chip Select
Single-Chip IEEE 802.11b/g/n 2T2R WLAN Controller
with PCI Express Interface
7
Track ID: Rev.0.1

11 Page







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